240-MHz 32-bit RX MCU, on-chip FPU, 480 DMIPS, 512-KB SRAM, various communications interfaces including IEEE 1588-compliant Ethernet MAC, high-speed USB 2.0 with battery charging, SD host interface (optional), quad SPI, and CAN, 12-bit A/D converter, RTC, encryption (optional), serial interface for audio, CMOS camera interface.
32-bit RXv2 CPU core Max. operating frequency: 240 MHz Capable of 480 DMIPS in operation at 240 MHz Single precision 32-bit IEEE-754 floating point Two types of multiply-and-accumulation unit (between memories and between registers) 32-bit multiplier (fastest instruction execution takes one CPU clock cycle) Divider (fastest instruction execution takes two CPU clock cycles) Fast interrupt CISC Harvard architecture with 5-stage pipeline Variable-length instructions: Ultra-compact code Supports the memory protection unit (MPU) JTAG and FINE (one-line) debugging interfaces Low-power design and architecture Operation from a single 2.7- to 3.6-V supply Low power consumption: A product that supports all peripheral functions draws only 0.2mA/MHz (Typ.). RTC is capable of operation from a dedicated power supply. Four low-power modes On-chip code flash memory Supports 4 Mbytes of ROM No wait states at up to 120 MHz or when the AFU is hit, one wait state at above 120 MHz and when the AFU is missed User code is programmable by on-board or off-board programming. Programming/erasing as background operations (BGOs) On-chip data flash memory 64 Kbytes, reprogrammable up to 100,000 times Programming/erasing as background operations (BGOs) On-chip SRAM 512 Kbytes of SRAM (no wait states except in the 256 Kbytes from 0004 0000h to 0007 FFFFh when ICLK is set to 120 MHz or faster) 32 Kbytes of RAM with ECC (single-error correction and double error detection) 8 Kbytes of standby RAM (backup on deep software standby) Package : LFBGA