HD6433048SB40FV by Renesas Electronics | 16 Bit Microcontrollers | Avnet EMEA
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HD6433048SB40FV

Renesas Electronics

MCU 16-Bit H8 H8/300H CISC 128KB ROM 5V 100-Pin FQFP

Manufacturer Part #: HD6433048SB40FV

Avnet Manufacturer Part #: HD6433048SB40FV


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Information

The H8/3048 Group is a series of microcontrollers (MCUs) that integrate system supporting functions together with an H8/300H CPU core having an original Renesas Technology architecture.The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address space. Its instruction set is upward-compatible at the object-code level with the H8/300 CPU, enabling easy porting of software from the H8/300 Series.The on-chip system supporting functions include ROM, RAM, a 16-bit integrated timer unit (ITU), a programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication interface (SCI), an A/D converter, a D/A converter, I/O ports, a direct memory access controller (DMAC), a refresh controller, and other facilities.

Key Features

  • CPU Upward-compatible with the H8/300 CPU at the object-code level
    • General-register machine
    • Sixteen 16-bit general registers
    • High-speed operation (flash memory version)
    • High-speed operation (mask ROM and PROM versions)
    • Maximum clock rate: 18 MHz
    • Add/subtract: 111 ns
    • Multiply/divide: 778 ns
    • 16-Mbyte address space
    • Instruction features
    • 8/16/32-bit data transfer, arithmetic, and logic instructions
    • Signed and unsigned multiply instructions (8 bits × 8 bits, 16 bits × 16 bits)
    • Signed and unsigned divide instructions (16 bits ˜ 8 bits, 32 bits ˜ 16 bits)
    • Bit accumulator function
    • Bit manipulation instructions with register-indirect specification of bit positions
  • Memory
    • ROM: 96 kbytes
    • RAM: 4 kbytes
  • Interrupt controller
    • Seven external interrupt pins: NMI, IRQ0 to IRQ5
    • 30 internal interrupts
    • Three selectable interrupt priority levels
  • Bus controller
    • Address space can be partitioned into eight areas, with independent bus specifications in each area
    • Chip select output available for areas 0 to 7
    • 8-bit access or 16-bit access selectable for each area
    • Two-state or three-state access selectable for each area
    • Selection of four wait modes
    • Bus arbitration function
  • Refresh controller
    • DRAM refresh
    • Directly connectable to 16-bit-wide DRAM
    • CAS-before-RAS refresh
    • Self-refresh mode selectable
    • Pseudo-static RAM refresh
    • Self-refresh mode selectable
    • Usable as an interval timer
  • DMA controller (DMAC)
    • Short address mode
    • Full address mode

Technical Attributes

Description
Value
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Number of Programmable I/Os
70
Device Core
H8/300H
RAM Size
4 KB
Maximum Speed
25 MHz
Supplier Package
FQFP
Product Dimensions
14 x 14 x 2.7
Lead Finish
Tin|Lead
Maximum Operating Supply Voltage
5.5 V
Watchdog
1
Pin Count
100
Operating Temperature
-20 to 75 °C
Mounting
Surface Mount
Interface Type
SCI/UART
Program Memory Size
128 KB
Maximum Expanded Memory Size
16 MB
Operating Supply Voltage
5 V
Instruction Set Architecture
CISC
Minimum Operating Supply Voltage
4.5 V
Number of Timers
5
On-Chip ADC
8-chx10-bit
Max Processing Temp
245
MSL Level
3
Data Bus Width
16 Bit

ECCN / UNSPSC

Description
Value
ECCN:
EAR99
UNSPSC:
32101640
UNSPSC VERSION:
V15.1101
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