The SMSC LAN91C111 is designed to facilitate the implementation of a third generation of Fast Ethernet connectivity solutions for embedded applications. For this third generation of products, flexibility and integration dominate the design requirements. The LAN91C111 is a mixed signal Analog/Digital device that implements the MAC and PHY portion of the CSMA/CD protocol at 10 and 100 Mbps. The design will also minimize data throughput constraints utilizing a 32-bit, 16-bit or 8-bit bus Host interface in embedded applications.
The total internal memory FIFO buffer size is 8 Kbytes, which is the total chip storage for transmit and receive operations.
The SMSC LAN91C111 is software compatible with the LAN9000 family of products.
Memory management is handled using a patented optimized MMU architecture and a 32-bit wide internal data path. This I/O mapped architecture can sustain back-to back frame transmission and reception for superior data throughput and optimal performance. It also dynamically allocates buffer memory in an efficient buffer utilization scheme, reducing software tasks and relieving the host CPU from performing these housekeeping functions.
The SMSC LAN91C111 provides a flexible slave interface for easy connectivity with industry-standard buses. The Bus Interface Unit (BIU) can handle synchronous as well as asynchronous transfers, with different signals being used for each one. Asynchronous bus support for ISA is supported even though ISA cannot sustain 100 Mbps traffic. Fast Ethernet data rates are attainable for ISA-based nodes on the basis of the aggregate traffic benefits.
Two different interfaces are supported on the network side. The first Interface is a standard Magnetics transmit/receive pair interfacing to 10/100Base-T utilizing the internal physical layer block. The second interface follows the MII specification standard, consisting of 4 bit wide data transfers at the nibble rate. This interface is applicable to 10 Mbps standard Ethernet or 100 Mbps Ethernet networks. Three of the LAN91C111's pins are used to interface to the two-line MII serial management protocol.
Single Chip Ethernet Controller
Fully Supports Full Duplex Switched Ethernet
Supports Burst Data Transfer
8 Kbytes Internal Memory for Receive and Transmit FIFO Buffers
Enhanced Power Management Features
Optional Configuration via Serial EEPROM Interface
Supports 8, 16 and 32 Bit CPU Accesses
Internal 32 Bit Wide Data Path (Into Packet Buffer Memory)
Built-in Transparent Arbitration for Slave Sequential Access Architecture
Flat MMU Architecture with Symmetric Transmit and Receive Structures and Queues
3.3V Operation with 5V Tolerant IO Buffers (See Pin List Description for Additional Details)
Single 25 MHz Reference Clock for Both PHY and MAC
External 25Mhz-output pin for an external PHY supporting PHYs physical media
Low Power CMOS Design
Supports Multiple Embedded Processor Host Interfaces — ARM — SH — Power PC — Coldfire — 680X0, 683XX — MIPS R3000
3.3V MII (Media Independent Interface) MAC-PHY Interface Running at Nibble Rate
MII Management Serial Interface
128-Pin QFP lead-free RoHS compliant package
128-Pin TQFP 1.0 mm height lead-free RoHS compliant package
Commercial Temperature Range from 0°C to 70°C (LAN91C111)
Industrial Temperature Range from -40°C to 85°C (LAN91C111i)