The KSZ8851M-series is a single-port controller chip with a non--PCI CPU interface and is available in 8/16-bit and 32-bit bus designs. The KSZ8851M offers the most cost-effective solution for adding high-throughput Ethernet connectivity to traditional embedded systems.
The KSZ8851M is a single chip, mixed analog/digital device offering Wake-on-LAN technology for effectively addressing Fast Ethernet applications. It consists of a Fast Ethernet MAC controller, an 8-bit, 16-bit and 32-bit generic host processor interface and incorporates a unique dynamic memory pointer with 4-byte buffer boundary and a fully utilizable 18KB for both TX (allocated 6KB) and RX (allocated 12KB) directions in host buffer interface.
The KSZ8851M is designed to be fully compliant with the appropriate IEEE 802.3 standards.
Physical signal transmission and reception are enhanced through the use of analog circuitry, making the design more efficient and allowing for lower-power consumption.
The KSZ8851M is designed using a low-power CMOS process that features a single 3.3V power supply with options for 1.8V, 2.5V or 3.3V Vdd I/O. The device includes an extensive feature set that offers management information base (MIB) counters and CPU control/data interfaces with single bus timing. The KSZ8851M includes unique cable diagnostics feature called LinkMD. This feature determines the length of the cabling plant and also ascertains if there is an open or short condition in the cable. Accompanying software enables the cable length and cable conditions to be conveniently displayed. In addition, the KSZ8851M supports Auto-MDIX thereby eliminating the need to differentiate between straight or crossover cables in applications.
Integrated MAC and PHY Ethernet Controller fully compliant with IEEE 802.3/802.3u standards
Designed for high performance and high throughput applications
Supports IEEE 802.3x full-duplex flow control and half duplex backpressure collision flow control
Supports DMA-slave burst data read and write transfers
Supports IP Header (IPv4)/TCP/UDP/ICMP checksum generation and checking
Supports IPv6 TCP/UDP/ICMP checksum generation and checking
Automatic 32-bit CRC generation and checking
Simple SRAM-like host interface easily connects to most common embedded MCUs
Supports multiple data frames for transmit and receive without address bus and byte-enable signals
Supports both Big
and Little-Endian processors
Larger internal memory with 12K Bytes for RX FIFO and 6K Bytes for TX FIFO. Programmable low, high and overrun watermark for flow control in RX FIFO
Efficient architecture design with configurable host interrupt schemes to minimize host CPU overhead and utilization
Powerful and flexible address filtering scheme
Optional to use external serial EEPROM configuration for both KSZ8851-16MQL and KSZ8851-32MQL
Single 25 MHz reference clock for both PHY and MAC