The IS61WV6416DBLLare high-speed, 1,048,576-bit static RAMs organized as 65,536 words by 16 bits. It is fabricated using high performance CMOS technology.This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices. When CE\ is HIGH (deselected), the device assumes a standby mode at which the power dpation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE\ and OE\. The active LOW Write Enable (WE\) controls both writing and reading of the memory. A data byte allows Upper Byte (UB\) and Lower Byte (LB\) access. The IS61WV6416DBLL are packaged in the JEDEC standard 44-pin TSOP Type II, 44-pin 400-mil SOJ and 48-pin Mini BGA (6mm x 8mm) .
High-speed access time: 8, 10, 12, 20 ns
Low Active Power: 135 mW (typical)
Low Standby Power: 12 µW (typical) CMOS standby
Single power supply: Vdd 2.4V to 3.6V
Fully static operation: no clocks or refresh required