The PI6C20400B is a PCIe 3.0 compliant high-speed, low-noise differential clock buffer designed to be companion to PCIe 3.0 clock generator. It is backward compatible with PCIe 1.0 and 2.0 specification. The device distributes the differential SRC clock from PCIe 3.0 clock generator to four differential pairs of clock outputs either with or without PLL. The clock outputs are controlled by input selection of SRC_STOP#, PWRDWN# and SMBus, SCLK and SDA. When input of either SRC_STOP# or PWRDWN# is low, the output clocks are Tristated. When PWRDWN# is low, the SDA and SCLK inputs must be Tri-stated.
Phase jitter filter for PCIe 3.0 application Four Pairs of Differential Clocks Low skew < 50ps Low jitter < 50ps cycle-to-cycle < 1 ps additive RMS phase jitter Output Enable for all outputs Outputs tristate control via SMBus Programmable PLL Bandwidth 100 MHz PLL Mode operation 100 - 400 MHz Bypass Mode operation 3.3V Operation