The 74HC595 is a high speed CMOS device. An eight bit shift register accepts data from the serial input (DS) on each positive transition of the shift register clock (SHCP). When asserted low, the shift register reset function (SHR) sets all shift register values to zero and is independent of all clocks. Also when asserted low, the storage register reset function (STR) sets all shift register values to zero and is independent of all clocks.Data from the input serial shift register is placed in the output register with a rising pulse on the storages resister clock (STCP). The storage resister includes output Q7S which is used for cascading information between devices. As the information moves into the storage register, it is asserted on the push-pull outputs Q0-Q7.All registers capture data on rising edge and change output on the falling edge. If both clocks are connected together, the input shift register is always one clock cycle ahead of the output register.