The PCI 9050-1 provides a compact high performance PCI bus target (slave) interface for adapter boards. The PCI 9050-1 is designed to connect a wide variety of local bus designs to the PCI bus and allow relatively slow local bus designs to achieve 132 MB/sec burst transfers on the PCI bus. The PCI 9050-1 can be programmed to connect directly to the multiplexed or nonmultiplexed 8, 16, or 32 bit local bus. The 8- and 16-bit modes enable easy conversion of ISA designs to PCI. The PCI 9050-1 contains a bidirectional FIFO to speed match the 32-bit wide, 33 MHz PCI bus to a local bus, which may be narrower or slower. Up to five local address spaces and up to four chip selects are supported.
PCI Specification 2.1 compliant. The PCI 9050-1 is compliant with PCI Specification 2.1, supporting low cost slave adapters. The chip allows simple conversion of ISA adapters to PCI.
Direct slave (Target) data transfer mode. The PCI 9050-1 supports memory mapped and I/O mapped burst accesses from the PCI bus to the local bus. Bidirectional FIFOs enable high-performance bursting on the local and PCI buses. The PCI bus is always bursting; however, the local bus can be set to bursting or continuous single cycle.
Interrupt generator. The PCI 9050-1 can generate a PCI interrupt from two local bus interrupt inputs.
Clock. The PCI 9050-1 local bus interface runs from a local TTL clock and generates the necessary internal clocks. This clock runs asynchronously to the PCI clock, allowing the local bus to run at an independent rate from the PCI clock. The buffered PCI bus clock (BCLKo) may be connected to the local bus clock (LCLK).
Programmable local bus configurations. The PCI 9050-1 supports 8, 16, or 32 bit local buses, which may be multiplexed or nonmultiplexed. The PCI 9050-1 has four byte enables (LBE[3:0]), 26 address lines (LA[27:2]), and 32, 16, or 8 bit data lines (LAD[31:0]).
Bus drivers. All control, address, and data signals generated by the PCI 9050-1 directly drive the PCI and local bus, without external drivers.
Serial EEPROM interface. The PCI 9050-1 contains an optional serial EEPROM interface, which can be used to load configuration information. This is useful for loading information unique to a particular adapter (such as Network ID, Vendor ID, and chip selects).
Four local chip selects. The PCI 9050-1 provides up to four local chip selects. The base address and range of each chip select are independently programmable from the EEPROM or host.
Five local address spaces. The base address and range of each local address space are independently programmable from the EEPROM or host.
Big/Little Endian byte swapping. The PCI 9050-1 supports Big and Little Endian byte ordering. The PCI 9050-1 also supports Big Endian byte lane mode to redirect the current word/byte lane during 16 or 8 bit local bus operation.
Read/write strobe delay and write cycle hold. The Read and Write (RD# and WR#) signals can be delayed from the beginning of the cycle for legacy interfaces (such as ISA bus).
Local bus wait states. In addition to the LRDYi# (local ready input) handshake signal for variable wait state generations, the PCI 9050-1 has an internal wait state(s) generator (R/W address to data, R/W data-to-data, and R/W data-to-address).
Programmable prefetch counter. The local bus prefetch counter can be programmed for 0 (no prefetch), 4, 8, 16, or continuous (prefetch counter turned off) Prefetch mode. The prefetched data can be used as cached data if a consecutive address is used (must be longword (Lword) aligned).