XC2C512-10FGG324C by Xilinx | CPLD | Avnet EMEA
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XC2C512-10FGG324C

Xilinx

CPLD CoolRunner -II Family 12K Gates 512 Macro Cells 128MHz 0.18um (CMOS) Technology 1.8V 324-Pin F-BGA

Manufacturer Part #: XC2C512-10FGG324C

Alternate Part #: XC2C512-10FGG324C


legend RoHS Compliant

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The CoolRunner-II 512-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved. This device consists of thirty two Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins. Clocking is available on a global or Function Block basis. Three global clocks areavailable for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-Function Block basis. A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device. Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies. The use of the clock divide (division by 2) and DualEDGE flip-flop gives the resultant CoolCLOCK feature. DataGATE is a method to selectively disable inputs of the CPLD that are not of interest during certain points in time. By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching. Another feature that eases voltage translation is I/O banking. Four I/O banks are available on the CoolRunner-II 512 macrocell device that permits easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices.

Key Features

  • Optimized for 1.8V systems
    • As fast as 7.1 ns pin-to-pin delays
    • As low as 14 μA quiescent current
  • Industry’s best 0.18 micron CMOS CPLD
    • Optimized architecture for effective logic synthesis
    • Multi-voltage I/O operation — 1.5V to 3.3V
  • Available in multiple package options
    • 208-pin PQFP with 173 user I/O
    • 256-ball FT (1.0mm) BGA with 212 user I/O
    • 324-ball FG (1.0mm) BGA with 270 user I/O
    • Pb-free available for all packages
  • Advanced system features
    • Fastest in system programming · 1.8V ISP using IEEE 1532 (JTAG) interface
    • IEEE1149.1 JTAG Boundary Scan Test
    • Optional Schmitt-trigger input (per pin)
    • Unsurpassed low power management · DataGATE enable signal control
    • Four separate I/O banks
    • RealDigital 100% CMOS product term generation
    • Flexible clocking modes · Optional DualEDGE triggered registers · Clock divider (divide by 2,4,6,8,10,12,14,16) · CoolCLOCK
    • Global signal options with macrocell control · Multiple global clocks with phase selection per macrocell · Multiple global output enables · Global set/reset
    • Advanced design security
    • PLA architecture · Superior pinout retention · 100% product term routability across function block
    • Open-drain output option for Wired-OR and LED drive
    • Optional bus-hold, 3-state or weak pullup on selected I/O pins
    • Optional configurable grounds on unused I/Os
    • Mixed I/O voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels · SSTL2-1, SSTL3-1, and HSTL-1 I/O compatibility
    • Hot Pluggable

Technical Attributes

Description
Value
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Maximum Operating Frequency
128 MHz
Typical Operating Supply Voltage
1.8 V
Mounting
Surface Mount
Speed Grade
10
Number of Macro Cells
512
Maximum Propagation Delay Time
10 ns
Re-programmability Support
No
Device System Gates
12000
Operating Temperature
0 to 70 °C
Screening Level
Commercial
Lead Finish
Tin/Silver/Copper
Maximum Operating Supply Voltage
1.9 V
Number of Logic Blocks/Elements
32
Number of Product Terms per Macro
40
In System Programmability
Yes
Number of User I/Os
270
Individual Output Enable Control
No
Maximum Internal Frequency
166 MHz
Fabrication Technology
0.18um (CMOS)
Max Processing Temp
250
Minimum Operating Supply Voltage
1.7 V

ECCN / UNSPSC

Description
Value
ECCN:
3A991D
SCHEDULE B:
8542390000"
HTSN:
8542390001"
UNSPSC:
32101643
UNSPSC VERSION:
V15.1101

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