SN74AUC1G74DCUR by Texas Instruments | Flip Flop | Avnet EMEA
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SN74AUC1G74DCUR

Texas Instruments

Flip Flop D-Type Pos-Edge 1-Element 8-Pin VSSOP T/R

Manufacturer Part #: SN74AUC1G74DCUR

Alternate Part #: SN74AUC1G74DCUR


legend RoHS Compliant

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Information

This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

A low level at the preset (PRE\) or clear (CLR\) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE\ and CLR\ are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for higher frequencies, the CLR\ input overrides the PRE\ input when they are both low.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Key Features

  • Available in the Texas Instruments NanoFree™ Package
  • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • Ioff Supports Partial-Power-Down Mode Operation
  • Sub-1-V Operable
  • Max tpd of 1.5 ns at 1.8 V
  • Low Power Consumption, 10-µA Max ICC
  • ±8-mA Output Drive at 1.8 V
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Technical Attributes

    Description
    Value
    Find similar Parts
    Number of Channels per Chip
    1
    Maximum Propagation Delay Time @ Maximum CL
    2.4@1.8V|1.8@2.5V ns
    Maximum Low Level Output Current
    9 mA
    Bus Hold
    No
    Maximum High Level Output Current
    -9 mA
    Number of Element Inputs
    1
    Set/Reset
    Set/Reset
    Screening Level
    Commercial
    Triggering Type
    Positive-Edge
    Input Signal Type
    Single-Ended
    Mounting
    Surface Mount
    Typical Operating Supply Voltage
    1.8|2.5 V
    Output Signal Type
    Differential
    Fabrication Technology
    CMOS
    Number of Elements per Chip
    1
    Number of Element Outputs
    1
    Maximum Operating Supply Voltage
    2.7 V
    Maximum Quiescent Current
    0.01 mA
    Polarity
    Inverting/Non-Inverting
    Logic Function
    D-Type
    Propagation Delay Test Condition
    30 pF
    Minimum Operating Supply Voltage
    0.8 V
    Max Processing Temp
    260
    Lead Finish
    Gold
    Operating Temperature
    -40 to 85 °C

    ECCN / UNSPSC

    Description
    Value
    ECCN:
    EAR99
    SCHEDULE B:
    85423990000
    UNSPSC:
    32101634
    UNSPSC VERSION:
    V15.1101

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    Your Price:

    EUR    €0,17784

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  • Lead time: 6 weeks
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