SN74LVCZ16240ADGGR by Texas Instruments | APACBuffer and Line Driver | Avnet ASIA
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信息

SN74LVCZ16240ADGGR

Texas Instruments

Buffer/Line Driver 16-CH Inverting 3-ST CMOS 48-Pin TSSOP T/R

製造商產品編號: SN74LVCZ16240ADGGR

替代料號: SN74LVCZ16240ADGGR


legend 通過RoHS認證

描述

文檔

替代/替換

資料

This 16-bit buffer/driver is designed for 2.7-V to 3.6-V VCC operation.

The SN74LVCZ16240A is designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.

The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. This device provides inverting outputs.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

During power up or power down when VCC is between 0 and 1.5 V, the device is in the high-impedance state. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down (VCC = 0 V). The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

技術參數

  • Member of the Texas Instruments Widebus™ Family
  • Operates From 2.7 V to 3.6 V
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.2 ns at 3.3 V
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Supports Mixed-Mode Signal Operation on All Ports (5-V Input/Output Voltage With 3.3-V VCC)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 1000-V Charged-Device Model (C101)
  • 技術屬性

    描述
    尋找類似物料
    Number of Elements per Chip
    4
    MSL Level
    1
    Mounting
    Surface Mount
    Input Signal Type
    Single-Ended
    Product Dimensions
    12.5 x 6.1 x 1.15 mm
    Number of Inputs per Chip
    16
    Number of Output Enables per Chip
    4 Low
    Output Type
    3-State
    Typical Operating Supply Voltage
    3.3 V
    Supplier Package
    TSSOP
    Maximum Propagation Delay Time @ Maximum CL
    4.5@2.7V|4.2@3.3V ns
    Maximum Low Level Output Current
    24 mA
    Polarity
    Inverting
    Logic Function
    Buffer/Line Driver
    Minimum Operating Supply Voltage
    2.7 V
    Number of Channels per Chip
    16
    Fabrication Technology
    CMOS
    Maximum Operating Supply Voltage
    3.6 V
    Maximum Quiescent Current
    100 uA
    Pin Count
    48
    Max Processing Temp
    260
    Propagation Delay Test Condition
    50 pF
    Lead Finish
    Gold
    Tolerant I/Os
    5 V
    Bus Hold
    No
    Maximum High Level Output Current
    -24 mA
    Number of Outputs per Chip
    16

    ECCN/UNSPSC

    描述
    ECCN:
    EAR99
    計劃交貨期 B:
    8542390000
    HTSN:
    8542390000
    UNSPSC:
    32101600
    UNSPSC VERSION:
    V15.1101
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