SN74LVC2G132YZPR by Texas Instruments | APACGates & Inverters | Avnet ASIA
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SN74LVC2G132YZPR

Texas Instruments

NAND Gate 2-Element 2-IN CMOS 8-Pin DSBGA T/R

製造商產品編號: SN74LVC2G132YZPR

替代料號: SN74LVC2G132YZPR


通過RoHS認證

描述

文檔

替代/替換

資料

This dual 2-input NAND gate with Schmitt-trigger inputs is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G132 contains two inverters and performs the Boolean function Y = A ⋅ B\ or Y = A\ + B\ in positive logic. The device functions as two independent inverters, but because of Schmitt action, it has different input threshold levels for positive-going (VT+) and negative-going (VT-) signals.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device can be triggered from the slowest of input ramps and still give clean jitter-free output signals.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

技術參數

  • Available in Texas Instruments NanoFree Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 5.3 ns at 3.3 V
  • Low Power Consumption, 10-μA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial Power Down Mode, and Back Drive Protection
  • Support Translation Down (5V to 3.3V and 3.3V to 1.8V)
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • 技術屬性

    描述
    尋找類似物料
    Input Type
    Schmitt Trigger
    Fabrication Technology
    CMOS
    Operating Temperature
    -40 to 85 °C
    Supplier Package
    DSBGA
    Product Dimensions
    1.9 x 0.9 x 0.3 mm
    Pin Count
    8
    Max Processing Temp
    260
    Screening Level
    Commercial
    Minimum Operating Supply Voltage
    1.65 V
    Maximum Operating Supply Voltage
    5.5 V
    Maximum Propagation Delay Time @ Maximum CL
    6@3.3V|5@5V ns
    Maximum Quiescent Current
    10 uA
    Lead Finish
    Tin/Silver/Copper
    Mounting
    Surface Mount
    MSL Level
    1
    Logic Function
    NAND

    ECCN/UNSPSC

    描述
    ECCN:
    EAR99
    計劃交貨期 B:
    8542310000"
    UNSPSC:
    32101633
    UNSPSC VERSION:
    V15.1101

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