SN74AUC2G125DCUR by Texas Instruments | APACBuffers & Line Drivers | Avnet ASIA
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信息

SN74AUC2G125DCUR

Texas Instruments

Buffer/Line Driver 2-CH Non-Inverting 3-ST CMOS 8-Pin VSSOP T/R

製造商產品編號: SN74AUC2G125DCUR

替代料號: SN74AUC2G125DCUR


通過RoHS認證

描述

文檔

替代/替換

資料

This dual bus buffer gate is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.

The SN74AUC2G125 features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

技術參數

  • Available in the Texas Instruments NanoFree™ Package
  • Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
  • Ioff Supports Partial-Power-Down Mode Operation
  • Sub-1-V Operable
  • Max tpd of 1.8 ns at 1.8 V
  • Low Power Consumption, 10 µA at 1.8 V
  • ±8-mA Output Drive at 1.8 V
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • 技術屬性

    描述
    尋找類似物料
    Minimum Operating Supply Voltage
    0.8 V
    Propagation Delay Test Condition
    30 pF
    Fabrication Technology
    CMOS
    Lead Finish
    Gold
    MSL Level
    1
    Maximum Propagation Delay Time @ Maximum CL
    2.6@1.8V|1.8@2.5V ns
    Maximum Operating Supply Voltage
    2.7 V
    Operating Temperature
    -40 to 85 °C
    Maximum Quiescent Current
    10 uA
    Pin Count
    8
    Supplier Package
    VSSOP
    Number of Inputs per Chip
    2
    Product Dimensions
    2.3 x 2 x 0.85 mm
    Input Signal Type
    Single-Ended
    Number of Channels per Chip
    2
    Tolerant I/Os
    3.6 V
    Screening Level
    Commercial
    Number of Output Enables per Chip
    2 Low
    Maximum High Level Output Current
    -9 mA
    Number of Outputs per Chip
    2
    Logic Function
    Buffer/Line Driver
    Output Type
    3-State
    Number of Elements per Chip
    2
    Maximum Low Level Output Current
    9 mA
    Bus Hold
    No
    Typical Operating Supply Voltage
    1.8|2.5 V
    Polarity
    Non-Inverting
    Mounting
    Surface Mount
    Max Processing Temp
    260

    ECCN/UNSPSC

    描述
    ECCN:
    EAR99
    計劃交貨期 B:
    8542310000
    HTSN:
    8542.39.00.01
    UNSPSC:
    32101600
    UNSPSC VERSION:
    V15.1101

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