DS92001TMA/NOPB by Texas Instruments | APACLVDS | Avnet ASIA
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信息

DS92001TMA/NOPB

Texas Instruments

LVDS Buffer 0.5V 8-Pin SOIC N

製造商產品編號: DS92001TMA/NOPB

替代料號: DS92001TMA/NOPB


legend 通過RoHS認證

描述

文檔

替代/替換

資料

The DS92001 B/LVDS-BLVDS Buffer takes a BLVDS input signal and provides a BLVDS output signal. In many large systems, signals are distributed across backplanes. One of the limiting factors for system speed is the "stub length" or the distance between the transmission line and the unterminated receivers on individual cards. Although it is generally recognized that this distance should be as short as possible to maximize system performance, real-world packaging concerns often make it difficult to make the stubs as short as the designer would like.

The DS92001 has edge transitions optimized for multidrop backplanes where the switching frequency is in the 200 MHz range or less. The output edge rate is critical in some systems where long stubs may be present, and utilizing a slow transition allows for longer stub lengths.

The DS92001, available in the WSON package, will allow the receiver inputs to be placed very close to the main transmission line, thus improving system performance.

A wide input dynamic range allows the DS92001 to receive differential signals from LVPECL, CML as well as LVDS sources. This will allow the device to also fill the role of an LVPECL-BLVDS or CML-BLVDS translator.

 

技術參數

  • Single +3.3 V Supply
  • Receiver Inputs Accept LVDS/CML/LVPECL Signals
  • TRI-STATE Outputs
  • Receiver Input Threshold < ±100 mV
  • Fast Propagation Delay of 1.4 ns (typ)
  • Low Jitter 400 Mbps Fully Differential Data Path
  • Compatible with BLVDS 10-bit SerDes (40MHz)
  • Compatible with ANSI/TIA/EIA-644-A LVDS Standard
  • Available in SOIC and Space Saving WSON Package
  • Industrial Temperature Range
  • 技術屬性

    描述
    尋找類似物料
    Transmission Data Rate
    400 Mbps
    Operating Temperature
    -40 to 85 °C
    Mounting
    Surface Mount
    Max Processing Temp
    260
    Supplier Package
    SOIC N
    MSL Level
    1
    Maximum Power Dissipation
    726 mW
    Lead Finish
    Matte Tin
    Differential Input Low Threshold Voltage
    -0.07 V
    Minimum Operating Supply Voltage
    3 V
    Maximum Operating Supply Voltage
    3.6 V
    Maximum Propagation Delay Time
    2 ns
    Screening Level
    Industrial
    Differential Input High Threshold Voltage
    -0.005 V
    Number of Drivers
    1
    Output Type
    Buffer
    Maximum Input Current
    20 uA
    Product Dimensions
    4.9 x 3.9 x 1.45 mm
    Number of Receivers
    1
    Input Type
    CML|LVDS|LVPECL
    Typical Operating Supply Voltage
    3.3 V
    Maximum Differential Output Voltage
    0.5 V
    Number of Elements per Chip
    1
    Pin Count
    8

    ECCN/UNSPSC

    描述
    ECCN:
    EAR99
    計劃交貨期 B:
    8542390000"
    HTSN:
    8542.39.00.01"
    UNSPSC:
    32101600
    UNSPSC VERSION:
    V15.1101
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