DS90UR906QSQE/NOPB by Texas Instruments | APACLVDS | Avnet ASIA
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信息

DS90UR906QSQE/NOPB

Texas Instruments

LVDS Deserializer 0.52V 60-Pin LLP EP T/R

製造商產品編號: DS90UR906QSQE/NOPB

替代料號: DS90UR906QSQE/NOPB


通過RoHS認證

描述

文檔

替代/替換

資料

The DS90UR905Q/906Q chipset translates a parallel RGB Video Interface into a high-speed serialized interface over a single pair. This serial bus scheme greatly eases system design by eliminating skew problems between clock and data, reduces the number of connector pins, reduces the interconnect size, weight, and cost, and overall eases PCB layout. In addition, internal DC balanced decoding is used to support AC-coupled interconnects.

The DS90UR905Q Ser (serializer) embeds the clock, balances the data payload, and level shifts the signals to high-speed low voltage differential signaling. Up to 24 inputs are serialized along with the three video control signals. This supports full 24-bit color or 18-bit color and 6 general purpose signals (e.g. Audio I2S) applications.

The DS90UR906Q Des (deserializer) recovers the data (RGB) and control signals and extracts the clock from the serial stream. It is able to lock to the incoming data stream without the use of a training sequence or special SYNC patterns, and does not require a reference clock. A link status (LOCK) output signal is provided.

Serial transmission is optimized by a user selectable de-emphasis, differential output level select features, and receiver equalization. EMI is minimized by the use of low voltage differential signaling, receiver drive strength control, and spread spectrum clocking compatibility. The Des may be configured to generate Spread Spectrum Clock and Data on its parallel outputs.

The DS90UR905Q (Ser) is offered in a 48-pin WQFN and the DS90UR906Q (Des) is offered in a 60-pin WQFN package. They are specified over the automotive AEC-Q100 grade 2 temperature range of -40°C to +105°C.

 

技術參數

  • 5 – 65 MHz PCLK Support (140 Mbps – 1.82 Gbps)
  • AC Coupled STP Interconnect Cable up to 10 Meters
  • Integrated Terminations on Ser and Des
  • @ Speed Link BIST Mode and Reporting Pin
  • Optional I2C Compatible Serial Control Bus
  • RGB888 + VS, HS, DE Support
  • Power Down Mode Minimizes Power Dissipation
  • 1.8V or 3.3V Compatible LVCMOS I/O Interface
  • Automotive Grade Product: AEC-Q100 Grade 2 Qualified
  • >8 kV HBM and ISO 10605 ESD Rating
  • Backward Compatible Mode for Operation with Older Generation Devices
  • SERIALIZER — DS90UR905Q

  • RGB888 + VS/HS/DE Serialized to 1 Pair FPD-Link II
  • Randomizer/Scrambler — DC-Balanced Data Stream
  • Selectable Output VOD and Adjustable De-Emphasis
  • DESERIALIZER — DS90UR906Q

  • FAST Random Data Lock; No Reference Clock Required
  • Adjustable Input Receiver Equalization
  • LOCK (Real Time Link Status) Reporting Pin
  • EMI Minimization on Output Parallel Bus (SSCG)
  • Output Slew Control (OS)
  • 技術屬性

    描述
    尋找類似物料
    Pin Count
    60
    MSL Level
    3
    Differential Input Low Threshold Voltage
    -0.05 V
    Output Type
    Deserializer
    Number of Elements per Chip
    1
    Maximum Differential Output Voltage
    0.52 V
    Screening Level
    Automotive
    Lead Finish
    Tin
    Maximum Power Dissipation
    470 mW
    Supplier Package
    LLP EP
    Number of Drivers
    24
    Product Dimensions
    9 x 9 x 0.8 mm
    Maximum Input Current
    15 uA
    Input Type
    FPD-Link II LVDS
    Maximum Operating Supply Voltage
    1.89 V
    Number of Receivers
    1
    Minimum Operating Supply Voltage
    1.71 V
    Typical Operating Supply Voltage
    1.8 V
    Mounting
    Surface Mount
    Max Processing Temp
    260
    Operating Temperature
    -40 to 105 °C
    Differential Input High Threshold Voltage
    0.05(Min) V

    ECCN/UNSPSC

    描述
    ECCN:
    EAR99
    計劃交貨期 B:
    8542.3200-00
    HTSN:
    8542.3200-00
    UNSPSC:
    32101600
    UNSPSC VERSION:
    V15.1101

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