DS90CR285MTD/NOPB by Texas Instruments | APACLVDS | Avnet ASIA
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信息

DS90CR285MTD/NOPB

Texas Instruments

LVDS 0.45V 56-Pin TSSOP Rail

製造商產品編號: DS90CR285MTD/NOPB

替代料號: DS90CR285MTD/NOPB


legend 通過RoHS認證

描述

文檔

替代/替換

資料

The DS90CR285 transmitter converts 28 bits of LVCMOS/LVTTL data into four LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fifth LVDS link. Every cycle of the transmit clock 28 bits of input data are sampled and transmitted. The DS90CR286 receiver converts the LVDS data streams back into 28 bits of LVCMOS/LVTTL data. At a transmit clock frequency of 66 MHz, 28 bits of TTL data are transmitted at a rate of 462 Mbps per LVDS data channel. Using a 66 MHz clock, the data throughput is 1.848 Gbit/s (231 Mbytes/s).

The multiplexing of the data lines provides a substantial cable reduction. Long distance parallel single-ended buses typically require a ground wire per active signal (and have very limited noise rejection capability). Thus, for a 28-bit wide data and one clock, up to 58 conductors are required. With the Channel Link chipset as few as 11 conductors (4 data pairs, 1 clock pair and a minimum of one ground) are needed. This provides a 80% reduction in required cable width, which provides a system cost savings, reduces connector physical size and cost, and reduces shielding requirements due to the cables' smaller form factor.

The 28 LVCMOS/LVTTL inputs can support a variety of signal combinations. For example, seven 4-bit nibbles or three 9-bit (byte + parity) and 1 control.

 

技術參數

  • Single +3.3V Supply
  • Chipset (Tx + Rx) Power Consumption <250 mW (typ)
  • Power-Down Mode (<0.5 mW total)
  • Up to 231 Megabytes/sec Bandwidth
  • Up to 1.848 Gbps Data Throughput
  • Narrow Bus Reduces Cable Size
  • 290 mV Swing LVDS Devices for Low EMI
  • +1V Common Mode Range (Around +1.2V)
  • PLL Requires no External Components
  • Both Devices are Offered in a Low Profile 56-Lead TSSOP Package
  • Rising Edge Data Strobe
  • Compatible with TIA/EIA-644 LVDS Standard
  • ESD Rating > 7 kV
  • Operating Temperature: −40°C to +85°C
  • 技術屬性

    描述
    尋找類似物料
    Number of Drivers
    4
    Maximum Operating Supply Voltage
    3.6 V
    Minimum Operating Supply Voltage
    3 V
    Product Dimensions
    14 x 6.1 x 0.9 mm
    Max Processing Temp
    260
    Lead Finish
    Matte Tin
    Maximum Input Current
    10 uA
    Input Type
    LVCMOS|LVTTL
    Mounting
    Surface Mount
    Transmission Data Rate
    1848 Mbps
    Typical Operating Supply Voltage
    3.3 V
    MSL Level
    2
    Differential Input High Threshold Voltage
    0.1 V
    Pin Count
    56
    Supplier Package
    TSSOP
    Maximum Power Dissipation
    1630 mW
    Number of Receivers
    28
    Maximum Differential Output Voltage
    0.45 V
    Operating Temperature
    -40 to 85 °C
    Differential Input Low Threshold Voltage
    -0.1 V
    Number of Elements per Chip
    4

    ECCN/UNSPSC

    描述
    ECCN:
    EAR99
    計劃交貨期 B:
    8542390000"
    UNSPSC:
    32101600
    UNSPSC VERSION:
    V15.1101

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