DS90CF388AVJD/NOPB by Texas Instruments | APACLVDS | Avnet ASIA
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信息

DS90CF388AVJD/NOPB

Texas Instruments

LVDS Flat Panel Display 0.45V 100-Pin TQFP Tray

製造商產品編號: DS90CF388AVJD/NOPB

替代料號: DS90CF388AVJD/NOPB


legend 通過RoHS認證

描述

文檔

替代/替換

資料

The DS90C387A/DS90CF388A transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL data and 3 control bits into 8 LVDS (Low Voltage Differential Signalling) data streams. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 784Mbps, providing a total throughput of 5.7Gbps (714 Megabytes per second).

The LDI chipset is improved over prior generations of FPD-Link devices and offers higher bandwidth support and longer cable drive. To increase bandwidth, the maximum pixel clock rate is increased to 112 MHz and 8 serialized LVDS outputs are provided. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects.

The DS90C387A transmitter provides a second LVDS output clock. Both LVDS clocks are identical. This feature supports backward compatibility with the previous generation of FPD-Link Receivers - the second clock allows the transmitter to interface to panels using a 'dual pixel' configuration of two 24-bit or 18-bit FPD-Link receivers.

This chipset is an ideal means to solve EMI and cable size problems for high-resolution flat panel applications. It provides a reliable interface based on LVDS technology that delivers the bandwidth needed for high-resolution panels while maximizing bit times, and keeping clock rates low to reduce EMI and shielding requirements.

技術參數

  • Supports SVGA through QXGA panel resolutions
  • 32.5 to 112/170MHz clock support
  • Drives long, low cost cables
  • Up to 5.7 Gbps bandwidth
  • Pre-emphasis reduces cable loading effects
  • Dual pixel architecture supports interface to GUI and timing controller; optional single pixel transmitter inputs support single pixel GUI interface
  • Transmitter rejects cycle-to-cycle jitter
  • 5V tolerant on data and control input pins
  • Programmable transmitter data and control strobe select (rising or falling edge strobe)
  • Backward compatible with FPD-Link
  • Compatible with ANSI/TIA/EIA-644-1995 LVDS Standard
  • 技術屬性

    描述
    尋找類似物料
    Maximum Input Current
    15 uA
    Mounting
    Surface Mount
    MSL Level
    3
    Number of Receivers
    8
    Typical Operating Supply Voltage
    3.3 V
    Differential Input High Threshold Voltage
    0.1 V
    Differential Input Low Threshold Voltage
    -0.1 V
    Pin Count
    100
    Input Type
    LVDS
    Product Dimensions
    14 x 14 x 1 mm
    Output Type
    Flat Panel Display
    Maximum Differential Output Voltage
    0.45 V
    Transmission Data Rate
    5700 Mbps
    Maximum Power Dissipation
    2800 mW
    Number of Drivers
    48
    Number of Elements per Chip
    8
    Minimum Operating Supply Voltage
    3 V
    Max Processing Temp
    260
    Supplier Package
    TQFP
    Lead Finish
    Tin
    Maximum Operating Supply Voltage
    3.6 V

    ECCN/UNSPSC

    描述
    ECCN:
    EAR99
    計劃交貨期 B:
    8542390000"
    UNSPSC:
    32101600
    UNSPSC VERSION:
    V15.1101

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