DP83816AVNG/NOPB by Texas Instruments | APACEthernet Controllers | Avnet ASIA
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信息

DP83816AVNG/NOPB

Texas Instruments

Ethernet CTLR Single Chip 10Mbps/100Mbps 3.3V 144-Pin LQFP Tray

製造商產品編號: DP83816AVNG/NOPB

替代料號: DP83816AVNG/NOPB


通過RoHS認證

描述

文檔

替代/替換

資料

DP83816 is a single-chip 10/100 Mb/s Ethernet Controller for the PCI bus. It is targeted at low-cost, high volume PC motherboards, adapter cards, and embedded systems. The DP83816 fully implements the V2.2 33 MHz PCI bus interface for host communications with power management support. Packet descriptors and data are transferred via bus-mastering, reducing the burden on the host CPU. The DP83816 can support full duplex 10/100 Mb/s transmission and reception, with minimum interframe gap.

The DP83816 device is an integration of an enhanced version of the National Semiconductor PCI MAC/BIU (Media Access Controller/Bus Interface Unit) and a 3.3V CMOS physical layer interface.

技術參數

  • IEEE 802.3 Compliant, PCI V2.2 MAC/BIU supports traditional data rates of 10 Mb/s Ethernet and 100 Mb/s Fast Ethernet (via internal phy)
  • Bus master - burst sizes of up to 128 dwords (512 bytes)
  • BIU compliant with PC 97 and PC 98 Hardware Design Guides, PC 99 Hardware Design Guide draft, ACPI v1.0, PCI Power Management Specification v1.1, OnNow Device Class Power Management Reference Specification - Network Device Class v1.0a
  • Wake on LAN (WOL) support compliant with PC98, PC99, SecureOn, and OnNow, including directed packets, Magic Packetš, VLAN packets, ARP packets, pattern match packets, and Phy status change
  • Clkrun function for PCI Mobile Design Guide
  • Virtual LAN (VLAN) and long frame support
  • Support for IEEE 802.3x Full duplex flow control
  • Extremely flexible Rx packet filtration including: single address perfect filter with MSb masking, broadcast, 512 entry multicast/unicast hash table, deep packet pattern matching for up to 4 unique patterns
  • Statistics gathered for support of RFC 1213 (MIB II), RFC 1398 (Ether-like MIB), IEEE 802.3 LME, reducing CPU overhead for management
  • Internal 2 KB Transmit and 2 KB Receive data FIFOs
  • Serial EEPROM port with auto-load of configuration data from EEPROM at power-on
  • Flash/PROM interface for remote boot support
  • Fully integrated IEEE 802.3/802.3u 3.3V CMOS physical layer
  • IEEE 802.3 10BASE-T transceiver with integrated filters
  • IEEE 802.3u 100BASE-TX transceiver
  • Fully integrated ANSI X3.263 compliant TP-PMD physical sublayer with adaptive equalization and Baseline Wander compensation
  • IEEE 802.3u Auto-Negotiation - advertised features configurable via EEPROM
  • Full Duplex support for 10 and 100 Mb/s data rates
  • Single 25 MHz reference clock
  • 144-pin LQFP and 160-pin LBGA packages
  • Low power 3.3V CMOS design with typical consumption of 561 mW operating, 380 mW during WOL mode, 33 mW sleep mode
  • IEEE 802.3u MII for connecting alternative external Physical Layer Devices
  •  

    技術屬性

    描述
    尋找類似物料
    Host Interface
    PCI
    Product Dimensions
    20 x 20 x 1.4 mm
    Auto-Negotiation
    Yes
    Loopback Mode
    Internal
    DMA Support
    Yes
    Network Interface
    MII
    Data Rate
    10|100 Mbps
    Communication Mode
    Full Duplex|Half Duplex
    Operating Supply Voltage
    3.3 V
    Category
    Single Chip
    Lead Finish
    Matte Tin

    ECCN/UNSPSC

    描述
    ECCN:
    EAR99
    計劃交貨期 B:
    8542390000
    HTSN:
    8542310000
    UNSPSC:
    32101600
    UNSPSC VERSION:
    V15.1101

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