This LSI is a microcomputer, featuring an LCD controller, USB host, and other peripheral functions. The SuperH RISC engine is a Renesas Technology-original 32-bit RISC (Reduced Instruction Set Computer) microcomputer. The SuperH RISC engine employs a fixed-length 16- bit instruction set, allowing an approximately 50% reduction in program size over a 32-bit instruction set. This LSI features the SH-4 CPU, which at the instruction set level is upwardly compatible with the SH-1, SH-2, and SH-3 microcomputers. This LSI has an instruction cache, an operand cache that can be switched between copy-back and write-through modes, a 4-entry full-associative instruction TLB (translation look aside buffer), and MMU (memory management unit) with 64- entry full-associative shared TLB. The sizes of the instruction cache and operand cache are 16 Kbytes and 32 Kbytes. This LSI also features the bus state controller (BSC) that can connect to synchronous DRAM. Also, because of its on-chip functions, such as an LCD controller, a USB host, timers, and serial communication functions, required for multimedia and OA equipment, this LSI enables a dramatic reduction in system costs.
Operating frequency: 200 MHz
Performance: 360MIPS, 1.4 GFLOPS
Voltage: 1.5 V (internal), 3.3 V (I/O)
Superscalar architecture: Parallel execution of two instructions