MC74LCX373DTR2G by ON Semiconductor | APACLatch | Avnet ASIA
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信息

MC74LCX373DTR2G

ON Semiconductor

Latch Transparent 3-ST 8-CH D-Type 20-Pin TSSOP T/R

製造商產品編號: MC74LCX373DTR2G

替代料號: MC74LCX373DTR2G


legend 通過RoHS認證

描述

文檔

替代/替換

資料

The MC74LCX373 is a high performance, non-inverting octal transparent latch operating from a 2.3 to 3.6 V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A V specification of 5.5 V allows MC74LCX373 inputs to be safely driven from 5 V devices. The MC74LCX373 contains 8 D-type latches with 3-state outputs. When the Latch Enable (LE) input is HIGH, data on the Dn inputs enters the latches. In this condition, the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LE. The 3-state standard outputs are controlled by the Output Enable (OEbar) input. When OEbar is LOW, the standard outputs are enabled. When OEbar is HIGH, the standard outputs are in the high impedance state, but this does not interfere with new data entering into the latches.

技術參數

  • Designed for 2.3 to 3.6V VCC Operation
  • 5V Tolerant Interface Capability With 5V TTL Logic
  • Supports Live Insertion and Withdrawal
  • IOFF Specification Guarantees High Impedance When VCC = 0V
  • LVTTL Compatible
  • LVCMOS Compatible
  • 24mA Balanced Output Sink and Source Capability
  • Near Zero Static Supply Current in All Three Logic States (10µA) Substantially Reduces System Power Requirements
  • Latchup Performance Exceeds 500mA
  • ESD Performance: Human Body Model >2000V; Machine Model >200V
  • Pb-Free Packages are Available*

技術屬性

描述
尋找類似物料
Propagation Delay Test Condition
50 pF
Maximum High Level Output Current
-24 mA
Mounting
Surface Mount
Polarity
Non-Inverting
Typical Operating Supply Voltage
2.5|3.3 V
Number of Input Enables per Element
1
Max Processing Temp
260
Latch Mode
Transparent
Number of Channels per Chip
8
Output Type
3-State
Maximum Low Level Output Current
24 mA
Product Dimensions
6.6 x 4.5 x 1.05 mm
Number of Outputs per Chip
8
Number of Output Enables per Element
1
Set/Reset
No
Operating Temperature
-40 to 85 °C
Pin Count
20
Maximum Quiescent Current
10 uA
Maximum Operating Supply Voltage
3.6 V
Fabrication Technology
CMOS
Number of Elements per Chip
1
Tolerant I/Os
5 V
MSL Level
1
Lead Finish
Gold
Bus Hold
No
Minimum Operating Supply Voltage
2 V
Supplier Package
TSSOP
Maximum Propagation Delay Time @ Maximum CL
9@2.7V|8@3.3V ns
Type
D-Type
Number of Inputs per Chip
8

ECCN/UNSPSC

描述
ECCN:
EAR99
計劃交貨期 B:
85423900228.1
HTSN:
85423900228.1
UNSPSC:
32101600
UNSPSC VERSION:
V15.1101
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