MC74HC73ADR2G by ON Semiconductor | APACFlip Flops | Avnet ASIA
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信息

MC74HC73ADR2G

ON Semiconductor

Flip Flop JK-Type Neg-Edge 2-Element 14-Pin SOIC T/R

製造商產品編號: MC74HC73ADR2G

替代料號: MC74HC73ADR2G


通過RoHS認證

描述

文檔

替代/替換

資料

High Performance Silicon Gate CMOS. The MC74HC73A is identical in pinout to the LS73. The device inputs are compatible with standard CMOS outputs, with pullup resistors, they are compatible with LSTTL outputs. Each flip flop is negative edge clocked and has an active low asynchronous reset. The MC74HC73A is identical in function to the HC107, but has a different pinout.

技術參數

  • Output Drive Capability: 10 LSTTL Loads
  • Outputs Directly Interface to CMOS, NMOS, and TTL
  • Operating Voltage Range: 2.0 to 6.0 V
  • Low Input Current: 1.0 µA
  • High Noise Immunity Characteristic of CMOS Devices
  • In Compliance with the JEDEC Standard No. 7.0 A Requirements
  • Chip Complexity: 92 FETs or 23 Equivalent Gates
  • These are PbFree Devices

技術屬性

描述
尋找類似物料
Number of Element Inputs
2
Product Dimensions
8.75 x 4 x 1.5 mm
Operating Temperature
-55 to 125 °C
Logic Function
JK-Type
Input Signal Type
Single-Ended
Number of Channels per Chip
2
Maximum Propagation Delay Time @ Maximum CL
125@2V|25@4.5V|21@6V ns
Polarity
Inverting/Non-Inverting
Triggering Type
Negative-Edge
Number of Elements per Chip
2
Typical Operating Supply Voltage
2.5|3.3|5 V
Bus Hold
No
Supplier Package
SOIC
Propagation Delay Test Condition
50 pF
Maximum Quiescent Current
0.004 mA
Max Processing Temp
260
Mounting
Surface Mount
Screening Level
Military
Maximum High Level Output Current
-5.2 mA
Maximum Low Level Output Current
5.2 mA
Set/Reset
Reset
Output Signal Type
Differential
Pin Count
14
Maximum Operating Supply Voltage
6 V
Lead Finish
Matte Tin
Number of Element Outputs
1
Fabrication Technology
CMOS
MSL Level
1
Minimum Operating Supply Voltage
2 V

ECCN/UNSPSC

描述
ECCN:
EAR99
計劃交貨期 B:
8542.33.00.00.0
HTSN:
8542.33.00.00.0
UNSPSC:
32101634
UNSPSC VERSION:
V15.1101
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