These dual N & P Channel logic level enhancement mode field effect transistors are produced using Fairchild 's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. The device is an improved design especially for low voltage applications as a replacement for bipolar digital transistors in load switching applications. Since bias resistors are not required, this dual digital FET can replace several digital transistors with difference bias resistors.
N-Channel 25 V, 0.22 A, R DS(ON) = 5 Ω @ V GS = 2.7 V.
P-Channel 25 V, -0.12 A , R DS(ON) = 13 Ω @ V GS = -2.7 V.
Very low level gate drive requirements allowing direct operation in 3 V circuits. V GS(th) < 1.5 V.
Gate-Source Zener for ESD ruggedness . >6 kV Human Body Model