TC850CPL by Microchip | APACADCs | Avnet ASIA
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信息

TC850CPL

Microchip

ADC Single Multi-Slope 40sps 15-bit+Sign Parallel 40-Pin PDIP Tube

製造商產品編號: TC850CPL

替代料號: TC850CPL


通過RoHS認證

描述

文檔

替代/替換

資料

The TC850 is a monolithic CMOS A/D converter (ADC) with resolution of 15-bits plus sign. It combines a chopper-stabilized buffer and integrator with a unique multiple-slope integration technique that increases conversion speed. The result is 16 times improvement in speed over previous 15-bit, monolithic integrating ADCs (from 2.5 conversions per second up to 40 per second). Faster conversion speed is especially welcome in systems with human interface, such as digital scales. The TC850 incorporates an ADC and a μP-compatible digital interface. Only a voltage reference and a few, noncritical, passive components are required to form a complete 15-bit plus sign ADC. CMOS processing provides the TC850 with high-impedance, differential inputs. Input bias current is typically only 30 pA, permitting direct interface to sensors. Input sensitivity of 100 μV per Least Significant bit (LSb) eliminates the need for precision external amplifiers. The internal amplifiers are auto-zeroed, ensuring a zero digital output, with 0V analog input. Zero adjustment potentiometers or calibrations are not required. The TC850 outputs data on an 8-bit, 3-state bus. Digital inputs are CMOS compatible while outputs are TTL/ CMOS compatible. Chip-enable and byte-select inputs, combined with an end-of-conversion output, ensures easy interfacing to a wide variety of microprocessors. Conversions can be performed continuously or on command. In Continuous mode, data is read as three consecutive bytes and manipulation of address lines is not required. Operating from ±5V supplies, the TC850 dissipates only 20 mΩ. The TC850 is packaged in a 40-pin plastic or ceramic dual-in-line package (DIPs) and in a 44-pin plastic leaded chip carrier (PLCC), surface-mount package.

技術參數

  • 15-bit Resolution Plus Sign Bit
  • Up to 40 Conversions per Second
  • Integrating ADC Technique: - Monotonic - High Noise Immunity - Auto-Zeroed Amplifiers Eliminate Offset Trimming
  • Wide Dynamic Range: 96 dB
  • Low Input Bias Current: 30 pA
  • Low Input Noise: 30 μVP-P
  • Sensitivity: 100 μV
  • Flexible Operational Control
  • Continuous or On Demand Conversions
  • Data Valid Output
  • Bus Compatible, 3-State Data Outputs: - 8-Bit Data Bus - Simple μP Interface - Two Chip Enables - Read ADC Result Like Memory
  • ± 5V Power Supply Operation: 20 mΩ
  • 40-Pin Dual-in-Line or 44-Pin PLCC Packages

技術屬性

描述
尋找類似物料
Resolution
15+Sign Bit
Input Signal Type
Differential
Differential Nonlinearity
±0.5 LSB
Mounting
Through Hole
Operating Temperature
0 to 70 °C
Supplier Package
PDIP
Digital Interface Type
Parallel
Number of ADCs
1
Input Voltage
3.277 V
Typical Dual Supply Voltage
±5 V
Max Processing Temp
260
Number of Analog Inputs
1
Pin Count
40
Single-Ended Input
No
Lead Finish
Matte Tin
Sampling Rate
40 sps
Architecture
Multi-Slope
Integral Nonlinearity Error
±2 LSB
Digital Supply Support
No
Maximum Power Dissipation
1230 mW
Sample and Hold
No
Polarity of Input Voltage
Unipolar
Differential Input
Yes
Voltage Reference
External
Voltage Supply Source
Dual
Product Dimensions
53.21 x 14.73 x 4.95 mm
Input Type
Voltage

ECCN/UNSPSC

描述
ECCN:
EAR99
計劃交貨期 B:
8542390000
HTSN:
8542390001
UNSPSC:
32101600
UNSPSC VERSION:
V15.1101
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