AS4C64M16D3-12BCN by Alliance Memory | APACDRAM Chip | Avnet ASIA
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信息

AS4C64M16D3-12BCN

Alliance Memory

DRAM Chip DDR3 SDRAM 1G-Bit 64M x 16 1.5V 96-Pin F-BGA

製造商產品編號: AS4C64M16D3-12BCN

替代料號: AS4C64M16D3-12BCN


legend 通過RoHS認證

描述

文檔

替代/替換

資料

The 1Gb Double-Data-Rate-3 DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM. The 1Gb chip is organized as 8Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer rates of up to 1600 Mb/sec/pin for general applications. The chip is designed to comply with all key DDR3 DRAM key features and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and CK# falling). All I/Os are synchronized with differential DQS pair in a source synchronous fashion. These devices operate with a single 1.5V ± 0.075V power supply and are available in BGA packages.

技術參數

  • JEDEC Standard Compliant
  • Power supplies: VDD & VDDQ = +1.5V  0.075V
  • Operating temperature:
    • Commercial (0 ~ 95°C)
    • Industrial (-40 ~ 95°C)
  • Supports JEDEC clock jitter specification
  • Fully synchronous operation
  • Fast clock rate: 800MHz
  • Differential Clock, CK & CK#
  • Bidirectional differential data strobe
    • DQS & DQS#
  • 8 internal banks for concurrent operation
  • 8n-bit prefetch architecture
  • Internal pipeline architecture
  • Precharge & active power down
  • Programmable Mode & Extended Mode registers
  • Additive Latency (AL): 0, CL-1, CL-2
  • Programmable Burst lengths: 4, 8
  • Burst type: Sequential / Interleave
  • Output Driver Impedance Control
  • 8192 refresh cycles / 64ms
    • Average refresh period
    • 7.8μs @ -40℃≦TC≦ +85℃
    • 3.9μs @ +85℃<TC≦ +95℃
  • Write Leveling
  • OCD Calibration
  • Dynamic ODT (Rtt_Nom & Rtt_WR)
  • RoHS compliant
  • Auto Refresh and Self Refresh
  • 96-ball 9 x 13 x 1.2mm FBGA package

技術屬性

描述
尋找類似物料
Number of Bits per Word
16 Bit
Organization
64M x 16
Address Bus Width
13 Bit
Operating Temperature
0 to 70 °C
Mounting
Surface Mount
Screening Level
Commercial
Supplier Package
FBGA
Density
1 Gb
Maximum Operating Current
65 mA
Number of Banks
8
Number of I/O Lines
16 Bit
Operating Supply Voltage
1.5 V
Maximum Clock Rate
800 MHz
Pin Count
96
Maximum Random Access Time
20 ns
Type
DDR3 SDRAM
Data Bus Width
16 Bit
Product Dimensions
9 x 13 x 1(Max)

ECCN/UNSPSC

描述
ECCN:
EAR99
計劃交貨期 B:
8542320040"
HTSN:
8542320040"
UNSPSC:
32101602
UNSPSC VERSION:
V15.1101
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