TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores with application specific coprocessors and I/O. KeyStone is the first of its kind that provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This is achieved with four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and HyperLink.
Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller enables processing cores to access shared memory directly without drawing from TeraNet’s capacity, so packet movement cannot be blocked by memory access.
HyperLink provides a 40-Gbaud chip-level interconnect that allows SoCs to work in tandem. Its lowprotocol overhead and high throughput make HyperLink an ideal interface for chip-to-chip interconnections. Working with Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are running on local resources.
One (C6655) or Two (C6657) TMS320C66x™ DSP Core Subsystems (CorePacs), Each With
850 MHz (C6657 only), 1.0 GHz, or 1.25 GHz C66x Fixed/Floating-Point CPU Core
40 GMAC/Core for Fixed Point @ 1.25 GHz
20 GFLOP/Core for Floating Point @ 1.25 GHz
Multicore Shared Memory Controller (MSMC)
1024KB MSM SRAM Memory (Shared by Two DSP C66x CorePacs for C6657)
Memory Protection Unit for Both MSM SRAM and DDR3_EMIF
8192 Multipurpose Hardware Queues with Queue Manager
Packet-Based DMA for Zero-Overhead Transfers
Two Viterbi Coprocessors
One Turbo Coprocessor Decoder
Four Lanes of SRIO 2.1
1.24/2.5/3.125/5 GBaud Operation Supported Per Lane
Supports Direct I/O, Message Passing
Supports Four 1×, Two 2×, One 4×, and Two 1× + One 2× Link Configurations
Single Port Supporting 1 or 2 Lanes
Supports Up To 5 GBaud Per Lane
Supports Connections to Other KeyStone Architecture Devices Providing Resource Scalability