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TMS320C6455BCTZA

Texas Instruments

DSP Fixed-Point 32-Bit 1GHz 8000MIPS 697-Pin FCBGA

制造商料号#: TMS320C6455BCTZA

替代型号#: TMS320C6455BCTZA


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描述

文档

替代/替换

信息

The TMS320C64x+ DSPs (including the TMS320C6455 device) are the highest-performance fixed-point DSP generation in the TMS320C6000 DSP platform. The C6455 device is based on the third-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for applications including video and telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+ devices are upward code-compatible from previous devices that are part of the C6000 DSP platform.

Based on 90-nm process technology and with performance of up to 9600 million instructions per second (MIPS) [or 9600 16-bit MMACs per cycle] at a 1.2-GHz clock rate, the C6455 device offers cost-effective solutions to high-performance DSP programming challenges. The C6455 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors.

The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles the multiply throughput versus the C64x core by performing four 16-bit x 16-bit multiply-accumulates (MACs) every clock cycle. Thus, eight 16-bit x 16-bit MACs can be executed every cycle on the C64x+ core. At a 1.2-GHz clock rate, this means 9600 16-bit MMACs can occur every second. Moreover, each multiplier on the C64x+ core can compute one 32-bit x 32-bit MAC or four 8-bit x 8-bit MACs every clock cycle.

The TCI6482 device includes Serial RapidIO®. This high bandwidth peripheral dramatically improves system performance and reduces system cost for applications that include multiple DSPs on a board, such as video and telecom infrastructures and medical/imaging.

技术参数

  • High-Performance Fixed-Point
    • 1.39-, 1.17-, 1-, 0.83-ns Instruction Time
    • 720-MHz, 850-MHz, 1-GHz, 1.2- Rate
    • Eight 32-Bit Instructions/Cycle
    • 9600 MIPS/MMACS (16-Bits)
    • Commercial Temperature [0°
    • Extended Temperature [-40°
  • TMS320C64x+™ DSP Core
    • Dedicated SPLOOP Instruction
    • Compact Instructions (16-Bit)
    • Instruction Set Enhancements
    • Exception Handling
  • TMS320C64x+ Megamodule L1/ Architecture:
    • 256K-Bit (32K-Byte) L1P Program [Direct Mapped]
    • 256K-Bit (32K-Byte) L1D Data [2-Way Set-Associative]
    • 16M-Bit (2048K-Byte) L2 Unified RAM/Cache [Flexible Allocation]
    • 256K-Bit (32K-Byte) L2 ROM
    • Time Stamp Counter
  • Enhanced Viterbi Decoder Coprocessor
    • Supports Over 694 7.95-Kbps
    • Programmable Code Parameters
  • Enhanced Turbo Decoder Coprocessor
    • Supports up to Eight 2-Mbps (6 Iterations)
    • Programmable Turbo Code Parameters
  • Endianess: Little Endian, Big
  • 64-Bit External Memory Interface
    • Glueless Interface to Asynchronous Memories (SRAM, Flash, and Synchronous Memories (SBSRAM, SRAM)
    • Supports Interface to Standard and Custom Logic (FPGA, CPLD, ASICs, etc.)
    • 32M-Byte Total Addressable Memory Space
  • Four 1x Serial RapidIO® Links v1.2 Compliant
    • 1.25-, 2.5-, 3.125-Gbps Link Rates
    • Message Passing, DirectIO Support, Error Mgmt Extensions, Congestion Control
    • IEEE 1149.6 Compliant I/Os
  • DDR2 Memory Controller
    • Interfaces to DDR2-533 SDRAM
    • 32-Bit/16-Bit, 533-MHz (data rate) Bus
    • 512M-Byte Total Addressable External Memory Space
  • EDMA3 Controller (64 Independent Channels)
  • 32-/16-Bit Host-Port Interface (HPI)
  • 32-Bit 33-/66-MHz, 3.3-V Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to PCI Local Bus Specification (
  • One Inter-Integrated Circuit (I2C) Bus
  • Two McBSPs
  • 10/100/1000 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports Multiple Media Independent Interfaces (MII, GMII, RMII, and RGMII)
    • 8 Independent Transmit (TX) and 8 Independent Receive (RX) Channels
  • Two 64-Bit General-Purpose Timers, Configurable as Four 32-Bit Timers
  • UTOPIA
    • UTOPIA Level 2 Slave ATM Controller
    • 8-Bit Transmit and Receive Operations 50 MHz per Direction
    • User-Defined Cell Format up to 64 Bytes
  • 16 General-Purpose I/O (GPIO) Pins
  • System PLL and PLL Controller
  • Secondary PLL and PLL Controller, Dedicated to EMAC and DDR2 Memory Controller
  • Advanced Event Triggering (AET) Compatible
  • Trace-Enabled Device
  • IEEE-1149.1 (JTAG™) Boundary-Scan- Compatible
  • 697-Pin Ball Grid Array (BGA) Package (CTZ, GTZ, or ZTZ Suffix), 0.8-mm Ball Pitch
  • 0.09-μm/7-Level Cu Metal Process (CMOS)
  • 3.3-/1.8-/1.5-/1.25-/1.2-V I/Os, 1.25-/1.2-V Internal

技术特性

描述
寻找类似物料
Lead Finish
Tin/Silver/Copper
Maximum Speed
1000 MHz
Device Input Clock Speed
1000 MHz
Mounting
Surface Mount
Data Bus Width
32 Bit
Supplier Package
FCBGA
Max Processing Temp
245
Pin Count
697
Product Dimensions
24.1 x 24.1 x 2.74 mm
MSL Level
4
Operating Supply Voltage
1.25|1.5|1.8|3.3 V
Numeric and Arithmetic Format
Fixed-Point
Instruction Set Architecture
Advanced VLIW
Device Million Instructions per Second
8000 MIPS

ECCN / UNSPSC

描述
ECCN:
3A991.a.2
计划交货期 B:
8542.2121-00
HTSN:
8542.2121-00
UNSPSC:
32101636
UNSPSC VERSION:
V15.1101

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