Buffer/Line Driver 2-CH Inverting 3-ST CMOS 8-Pin VSSOP T/R
This dual buffer driver is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC2G240 device is designed specifically to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is organized as two 1-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A input to the Y output. When OE is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.