SN74LVC2G125YZPR by Texas Instruments | APACBuffer and Line Driver | Avnet ASIA

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信息

SN74LVC2G125YZPR

Texas Instruments

Buffer/Line Driver 2-CH Non-Inverting 3-ST CMOS 8-Pin DSBGA T/R

制造商料号#: SN74LVC2G125YZPR

替代型号#: SN74LVC2G125YZPR


legend 通过RoHS认证

描述

文档

替代/替换

信息

The SN74LVC2G125 device is a dual bus buffer gate, designed for 1.65-V to 5.5-V VCC operation. This device features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable (OE) input is high.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

技术参数

  • Available in the Texas Instruments
    NanoFree™ Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.3 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    < 0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    > 2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down Mode,
    and Back-Drive Protection
  • Can Be Used as a Down Translator to Translate Inputs
    From a Max of 5.5 V Down to the VCC Level
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model
    • 200-V Machine Model
    • 1000-V Charged-Device Model
  • 技术特性

    描述
    寻找类似物料
    Product Dimensions
    1.9 x 0.9 x 0.3 mm
    Propagation Delay Test Condition
    50 pF
    Maximum Quiescent Current
    10 uA
    Maximum High Level Output Current
    -32 mA
    Maximum Operating Supply Voltage
    5.5 V
    Mounting
    Surface Mount
    Pin Count
    8
    Polarity
    Non-Inverting
    Maximum Low Level Output Current
    32 mA
    Input Signal Type
    Single-Ended
    Number of Output Enables per Chip
    2 Low
    Number of Outputs per Chip
    2
    Number of Inputs per Chip
    2
    Logic Function
    Buffer/Line Driver
    Output Type
    3-State
    Number of Elements per Chip
    2
    Maximum Propagation Delay Time @ Maximum CL
    4.3@3.3V|3.7@5V ns
    Minimum Operating Supply Voltage
    1.65 V
    Supplier Package
    DSBGA
    Number of Channels per Chip
    2
    Operating Temperature
    -40 to 85 °C
    Typical Operating Supply Voltage
    1.8|2.5|3.3|5 V
    Bus Hold
    No
    Fabrication Technology
    CMOS
    Tolerant I/Os
    5 V
    Max Processing Temp
    260
    Lead Finish
    Tin/Silver/Copper
    MSL Level
    1

    ECCN / UNSPSC

    描述
    ECCN:
    EAR99
    计划交货期 B:
    8542310000"
    UNSPSC:
    32101600
    UNSPSC VERSION:
    V15.1101

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