LMH1983SQ/NOPB by Texas Instruments | APACClock and Timing Misc | Avnet ASIA
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信息

LMH1983SQ/NOPB

Texas Instruments

Video Clock Generator 40-Pin LLP EP T/R

制造商料号#: LMH1983SQ/NOPB

替代型号#: LMH1983SQ/NOPB


legend 通过RoHS认证

描述

文档

替代/替换

信息

The LMH1983 is a highly-integrated programmable audio/video (A/V) clock generator intended for broadcast and professional applications. It can replace multiple PLLs and VCXOs used in applications supporting SMPTE serial digital video (SDI) and digital audio AES3/EBU standards. It offers low-jitter reference clocks for any SDI transmitter to meet stringent output jitter specifications without additional clock cleaning circuits.

The LMH1983 features automatic input format detection, simple programming of multiple A/V output formats, genlock or digital free-run modes, and override programmability of various automatic functions. The recognized input formats include HVF syncs for the major video standards, 27 MHz, 10 MHz, and 32/44.1/48/96 kHz audio word clocks.

The dual-stage PLL architecture integrates four PLLs with three on-chip VCOs. The first stage (PLL1) uses an external low-noise 27 MHz VCXO with narrow loop bandwidth to provide a clean reference clock for the next stage. The second stage (PLL2, 3, 4) consists of three parallel VCO PLLs for simultaneous generation of the major digital A/V clock fundamental rates, including 148.5 MHz, 148.5/1.001 MHz, and 98.304 MHz (4 × 24.576 MHz). Each PLL can generate a clock and a timing pulse to indicate top of frame (TOF).

When locked to reference, an internal 10-bit ADC will track the loop filter control voltage. When a loss of reference (LOR) occurs, the LMH1983 can be programmed to hold the control voltage to maintain output accuracy within ±0.5 ppm (typical) of the previous reference. The LMH1983 can be configured to re-synchronize to a previous reference with glitch-less operation.

 

技术参数

  • Four PLLs for Simultaneous A/V Clock Generation
    • PLL1: 27 or 13.5 MHz
    • PLL2: 148.5 or 74.25 MHz
    • PLL3: 148.5/1.001 or 74.25/1.001 MHz
    • PLL4: 98.304 MHz / 2X (X = 0 to 15)
  • 3 x 2 Video Clock Crosspoint
  • Flexible PLL Bandwidth to Optimize Jitter Performance
    and Lock Time
  • Soft Resynchronization to New Reference
  • Digital Holdover or Free-run on Loss of Reference
  • Status Flags for Loss of Reference and Loss of PLL Lock
  • 3.3 V Single Supply Operation
  • I2C Interface with Address Select Pin
    (3 States)
  • 技术特性

    描述
    寻找类似物料
    Operating Temperature
    -40 to 85 °C
    Supplier Package
    LLP EP
    Product Dimensions
    6 x 6 x 0.8 mm
    Pin Count
    40
    Mounting
    Surface Mount
    MSL Level
    3
    Max Processing Temp
    260
    Category
    Video Clock Generator
    Lead Finish
    Matte Tin

    ECCN / UNSPSC

    描述
    ECCN:
    EAR99
    计划交货期 B:
    8542390000"
    HTSN:
    8542390001"
    UNSPSC:
    32101600
    UNSPSC VERSION:
    V15.1101

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