DP83848KSQ/NOPB by Texas Instruments | APACPHY | Avnet ASIA
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信息

DP83848KSQ/NOPB

Texas Instruments

PHY 1-CH 10Mbps/100Mbps 40-Pin LLP EP T/R

制造商料号#: DP83848KSQ/NOPB

替代型号#: DP83848KSQ/NOPB


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描述

文档

替代/替换

信息

The DP83848x device addresses the quality, reliability and small form factor required for space sensitive applications in embedded systems.

The DP83848x offers performance far exceeding the IEEE specifications, with superior interoperability and industry leading performance beyond 137 meters of Cat-V cable. The DP83848x also offers Auto-MDIX to remove cabling complications. DP83848x has superior ESD protection, greater than 4 kV Human Body Model, providing extremely high reliability and robust operation, ensuring a high-level performance in all applications.

DP83848J/K offers two flexible LED indicators one for Link and the other for Speed. In addition, both MII and RMII are supported ensuring ease and flexibility of design.

The DP83848H/M/T incorporates a 25-MHz clock out that eliminates the need and hence the space and cost, of an additional clock source component.

The DP83848x is offered in small 6-mm × 6-mm WQFN 40-pin package and is ideal for industrial controls, building/factory automation, transportation, test equipment and wire-less base stations.

技术参数

  • Low-Power 3.3-V, 0.18-µm CMOS Technology
  • Auto-MDIX for 10/100 Mb/s
  • Energy Detection Mode
  • 3.3-V MAC Interface
  • RMII Rev. 1.2 Interface (configurable)
  • MII Interface
  • MII Serial Management Interface (MDC and MDIO)
  • IEEE 802.3 Auto-Negotiation and Parallel Detection
  • IEEE 802.3 ENDEC, 10BASE-T Transceivers and Filters
  • IEEE 802.3 PCS, 100BASE-TX Transceivers and Filters
  • Integrated ANSI X3.263 Compliant TP-PMD Physical
    Sub-Layer with Adaptive Equalization and Baseline
    Wander Compensation
  • Error-Free Operation Beyond 137 Meters
  • ESD Protection – Greater than 4 kV Human Body Model
  • Configurable LED for Link and Activity (DP83848J/K)
  • 25-MHz Clock Output (DP83848H/M/T)
  • Single Register Access for Complete PHY Status
  • 10/100 Mb/s Packet BIST (Built-in Self Test)
  • 技术特性

    描述
    寻找类似物料
    Product Dimensions
    6 x 6 x 0.8 mm
    PHY Line Side Interface
    No
    Maximum Single Supply Voltage
    3.6 V
    Supplier Package
    LLP EP
    MSL Level
    2
    Integrated CDR
    No
    Maximum Data Rate
    100 Mbps
    Max Processing Temp
    260
    Pin Count
    40
    JTAG Support
    No
    Standard Supported
    IEEE 802.3u
    UTOPIA Level
    No
    Overhead Octet Support
    No
    Maximum Supply Current
    92 mA
    Lead Finish
    Tin
    Mounting
    Surface Mount
    Number of Channels per Chip
    1
    Minimum Single Supply Voltage
    3 V

    ECCN / UNSPSC

    描述
    ECCN:
    EAR99
    计划交货期 B:
    8542390000"
    UNSPSC:
    32101600
    UNSPSC VERSION:
    V15.1101

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