MC100LVEL11DG by ON Semiconductor | APACClock Buffer | Avnet ASIA
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信息

MC100LVEL11DG

ON Semiconductor

Clock Fanout Buffer 4-OUT 8-Pin SOIC N Rail

制造商料号#: MC100LVEL11DG

替代型号#: MC100LVEL11DG


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描述

文档

替代/替换

信息

The MC100LVEL11 is a differential 1:2 fanout buffer. The device is functionally similar to the E111 device but with higher performance capabilities. Having within-device skews and output transition times significantly improved over the E111, the LVEL11 is ideally suited for those applications which require the ultimate in AC performance. The differential inputs of the LVEL11 employ clamping circuitry to maintain stability under open input conditions. If the inputs are left open (pulled to V) the Q outputs will go LOW.

技术参数

  • 330 ps Propagation Delay
  • 5 ps Skew Between Outputs
  • High Bandwidth Output Transitions
  • ESD Protection: >4 KV HBM, >200 V MM
  • The 100 Series Contains Temperature Compensation
  • PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with VEE= 0 V
  • NECL Mode Operating Range: VCC= 0 V with VEE = -3.0 V to -3.8 V
  • Internal Input Pulldown Resistors
  • Q Output will Default LOW with Inputs Open or at VEE
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Moisture Sensitivity Level 1
    For Additional Information, see Application Note AND8003/D
  • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
  • Transistor Count = 63 devices

技术特性

描述
寻找类似物料
Supplier Package
SOIC N
Operating Supply Voltage
-3.3|3.3 V
Maximum Operating Supply Voltage
-3.8|3.8 V
Mounting
Surface Mount
Max Processing Temp
260|265
Maximum Input Frequency
1000 MHz
MSL Level
1
Lead Finish
Matte Tin
Minimum Operating Supply Voltage
-3|3 V
Number of Outputs per Chip
4
Pin Count
8
Product Dimensions
5 x 4 x 1.5 mm
Maximum Propagation Delay Time @ Maximum CL
0.405@3.3V ns

ECCN / UNSPSC

描述
ECCN:
EAR99
计划交货期 B:
8542.2129-00
HTSN:
8542.2129-00
UNSPSC:
32101600
UNSPSC VERSION:
V15.1101
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