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SN74AVCH16T245VR

Texas Instruments

Bus XCVR Dual 16-CH 3-ST 48-Pin TVSOP T/R

制造商料号#: SN74AVCH16T245VR

替代型号#: SN74AVCH16T245VR


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描述

文档

替代/替换

信息

This 16-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVCH16T245 device is optimized to operate with VCCA/VCCB set at 1.4 V to 3.6 V. The device is operational with VCCA/VCCB as low as 1.2 V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2 V to 3.6 V. This allows for universal low-voltage bidirectional translation between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, and 3.3-V voltage nodes.

The SN74AVCH16T245 control pins (1DIR, 2DIR, 1OE, and 2OE) are supplied by VCCA.

The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. This device is fully specified for partial-power-down applications using Ioff.

The VCC isolation feature ensures that if either VCC input is at GND, then both ports are in the high-impedance state.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74AVCH16T245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the outputs so the buses are effectively isolated.

技术参数

  • Control Inputs VIH/VIL Levels Are Referenced to
    VCCA Voltage
  • VCC Isolation Feature – If Either VCC Input is at
    GND, Both Ports are in the High-Impedance State
  • Overvoltage-Tolerant Inputs and Outputs Allow
    Mixed Voltage-Mode Data Communications
  • Fully Configurable Dual-Rail Design Allows Each
    Port to Operate Over the Full 1.2 V to 3.6 V
    Power-Supply Range
  • Ioff Supports Partial-Power-Down Mode Operation
  • I/Os are 4.6 V Tolerant
  • Bus Hold on Data Inputs Eliminates the Need for
    External Pullup and Pulldown Resistors
  • Maximum Data Rates
    • 380 Mbps (1.8 V to 3.3 V Level-Shifting)
    • 200 Mbps (<1.8 V to 3.3 V Level-Shifting)
    • 200 Mbps (Level-Shifting to 2.5 V or 1.8 V)
    • 150 Mbps (Level-Shifting to 1.5 V)
    • 100 Mbps (Level-Shifting to 1.2 V)
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 8000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • 技术特性

    描述
    寻找类似物料
    Number of Elements per Chip
    2
    Polarity
    Non-Inverting
    Maximum Low Level Output Current
    12 mA
    Maximum Operating Supply Voltage
    3.6 V
    Output Level
    CMOS
    Input Level
    CMOS
    Number of Channels per Chip
    16
    Output Type
    3-State
    Max Processing Temp
    260
    Typical Operating Supply Voltage
    1.8|2.5|3.3 V
    Operating Temperature
    -40 to 85 °C
    Number of Output Enables per Element
    1 Low
    Lead Finish
    Gold
    Fabrication Technology
    CMOS
    Propagation Delay Test Condition
    15 pF
    Mounting
    Surface Mount
    Bus Hold
    Yes
    Logic Function
    Bus Transceiver with Voltage Translation
    Minimum Operating Supply Voltage
    1.2 V
    Screening Level
    Commercial
    Tolerant I/Os
    4.6 V
    Maximum Propagation Delay Time @ Maximum CL
    6.2@1.5V ns
    Number of Direction Control Inputs
    1 Low/High
    Data Flow Direction
    Bi-Directional
    Maximum High Level Output Current
    -12 mA

    ECCN / UNSPSC

    描述
    ECCN:
    EAR99
    计划交货期 B:
    8542.39.00.00
    HTSN:
    8542.39.00.00
    UNSPSC:
    32101654
    UNSPSC VERSION:
    V15.1101

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