TMS320C6657CZHA25 by Texas Instruments | DSP | Avnet ASIA

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TMS320C6657CZHA25

Texas Instruments

DSP Fixed-Point/Floating-Point 16-Bit 1250MHz 625-Pin FCBGA

Manufacturer Part #: TMS320C6657CZHA25

Alternate Part #: TMS320C6657CZHA25


legend RoHS Compliant

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Information

TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores with application specific coprocessors and I/O. KeyStone is the first of its kind that provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This is achieved with four main hardware elements: Multicore Navigator, TeraNet, Multicore Shared Memory Controller, and HyperLink.

Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller enables processing cores to access shared memory directly without drawing from TeraNet’s capacity, so packet movement cannot be blocked by memory access.

HyperLink provides a 40-Gbaud chip-level interconnect that allows SoCs to work in tandem. Its lowprotocol overhead and high throughput make HyperLink an ideal interface for chip-to-chip interconnections. Working with Multicore Navigator, HyperLink dispatches tasks to tandem devices transparently and executes tasks as if they are running on local resources.

Key Features

  • One (C6655) or Two (C6657) TMS320C66x™
    DSP Core Subsystems (CorePacs), Each With
    • 850 MHz (C6657 only), 1.0 GHz, or 1.25 GHz
      C66x Fixed/Floating-Point CPU Core
      • 40 GMAC/Core for Fixed Point @ 1.25 GHz
      • 20 GFLOP/Core for Floating Point @ 1.25
        GHz
  • Multicore Shared Memory Controller (MSMC)
    • 1024KB MSM SRAM Memory
      (Shared by Two DSP C66x CorePacs for
      C6657)
    • Memory Protection Unit for Both MSM SRAM
      and DDR3_EMIF
  • Multicore Navigator
    • 8192 Multipurpose Hardware Queues with
      Queue Manager
    • Packet-Based DMA for Zero-Overhead
      Transfers
  • Hardware Accelerators
    • Two Viterbi Coprocessors
    • One Turbo Coprocessor Decoder
  • Peripherals
    • Four Lanes of SRIO 2.1
      • 1.24/2.5/3.125/5 GBaud Operation
        Supported Per Lane
      • Supports Direct I/O, Message Passing
      • Supports Four 1×, Two 2×, One 4×, and Two
        1× + One 2× Link Configurations
    • PCIe Gen2
      • Single Port Supporting 1 or 2 Lanes
      • Supports Up To 5 GBaud Per Lane
    • HyperLink
      • Supports Connections to Other KeyStone
        Architecture Devices Providing Resource
        Scalability
      • Supports up to 40 Gbaud
    • Gigabit Ethernet (GbE) Subsystem
      • One SGMII Port
      • Supports 10/100/1000 Mbps Operation
    • 32-Bit DDR3 Interface
      • DDR3-1333
      • 8G Byte Addressable Memory Space
    • 16-Bit EMIF
    • Universal Parallel Port
      • Two Channels of 8 bits or 16 bits Each
      • Supports SDR and DDR Transfers
    • Two UART Interfaces
    • Two Multichannel Buffered Serial Ports
      (McBSP)
    • I2C Interface
    • 32 GPIO Pins
    • SPI Interface
    • Semaphore Module
    • Eight 64-Bit Timers
    • Two On-Chip PLLs
  • Commercial Temperature:
    • 0°C to 85°C
  • Extended Temperature:
    • – 40°C to 100°C
  • Extended Low Temperature:
    • – 55°C to 100°C
  • Technical Attributes

    Description
    Value
    Find similar Parts
    Supplier Package
    FCBGA
    Operating Supply Voltage
    1|1.5|1.8 V
    Mounting
    Surface Mount
    RAM Size
    1 MB
    Maximum Speed
    1250 MHz
    Device Input Clock Speed
    1250 MHz
    Numeric and Arithmetic Format
    Fixed-Point|Floating-Point
    Operating Temperature
    -40 to 100 °C
    Pin Count
    625
    MSL Level
    3
    Lead Finish
    Tin|Silver|Copper
    Max Processing Temp
    245
    Product Dimensions
    21(Max) x 21(Max) x 2.54(Max)
    Device Million Instructions per Second
    8000 MIPS
    Program Memory Size
    128 KB
    Data Bus Width
    16 Bit

    ECCN / UNSPSC

    Description
    Value
    ECCN:
    5A992.c
    SCHEDULE B:
    8504.4091-09
    HTSN:
    8504.4091-09
    UNSPSC:
    32101636
    UNSPSC VERSION:
    V15.1101

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