The TMS320C64x+ DSPs (including the TMS320C6455 device) are the highest-performance fixed-point DSP generation in the TMS320C6000 DSP platform. The C6455 device is based on the third-generation high-performance, advanced VelociTI very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for applications including video and telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+ devices are upward code-compatible from previous devices that are part of the C6000 DSP platform.
Based on 90-nm process technology and with performance of up to 9600 million instructions per second (MIPS) [or 9600 16-bit MMACs per cycle] at a 1.2-GHz clock rate, the C6455 device offers cost-effective solutions to high-performance DSP programming challenges. The C6455 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors.
The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles the multiply throughput versus the C64x core by performing four 16-bit x 16-bit multiply-accumulates (MACs) every clock cycle. Thus, eight 16-bit x 16-bit MACs can be executed every cycle on the C64x+ core. At a 1.2-GHz clock rate, this means 9600 16-bit MMACs can occur every second. Moreover, each multiplier on the C64x+ core can compute one 32-bit x 32-bit MAC or four 8-bit x 8-bit MACs every clock cycle.
The TCI6482 device includes Serial RapidIO®. This high bandwidth peripheral dramatically improves system performance and reduces system cost for applications that include multiple DSPs on a board, such as video and telecom infrastructures and medical/imaging.
1.39-, 1.17-, 1-, 0.83-ns Instruction Time
720-MHz, 850-MHz, 1-GHz, 1.2- Rate
Eight 32-Bit Instructions/Cycle
9600 MIPS/MMACS (16-Bits)
Commercial Temperature [0°
Extended Temperature [-40°
TMS320C64x+™ DSP Core
Dedicated SPLOOP Instruction
Compact Instructions (16-Bit)
Instruction Set Enhancements
TMS320C64x+ Megamodule L1/ Architecture:
256K-Bit (32K-Byte) L1P Program [Direct Mapped]
256K-Bit (32K-Byte) L1D Data [2-Way Set-Associative]