SNJ54ABT16373AWD by Texas Instruments | Latches | Avnet ASIA
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SNJ54ABT16373AWD

Texas Instruments

Latch Transparent 3-ST 16-CH D-Type 48-Pin CFPAK Tube

Manufacturer Part #: SNJ54ABT16373AWD

Alternate Part #: SNJ54ABT16373AWD


RoHS Compliant

Descriptions

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Information

The 'ABT16373A are 16-bit transparent D-type latches with 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN54ABT16373A is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT16373A is characterized for operation from -40°C to 85°C.

Key Features

  • Members of the Texas InstrumentsWidebusTM Family
  • State-of-the-ArtEPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
  • Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
  • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 5 V, TA = 25°C
  • High-Impedance State During Power Up and Power Down
  • Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • High-Drive Outputs (-32-mA IOH, 64-mA IOL)
  • Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
  • Technical Attributes

    Description
    Value
    Find similar Parts
    Supplier Package
    CFPAK
    Fabrication Technology
    BiCMOS
    Type
    D-Type
    Product Dimensions
    15.88 x 9.66 x 2.48 mm
    Maximum High Level Output Current
    -24 mA
    Lead Finish
    Tin/Lead
    Pin Count
    48
    Polarity
    Non-Inverting
    Operating Temperature
    -55 to 125 °C
    Number of Inputs per Chip
    16
    Maximum Quiescent Current
    85000 uA
    Typical Operating Supply Voltage
    5 V
    Maximum Propagation Delay Time @ Maximum CL
    5.4@5V ns
    Output Type
    3-State
    Number of Elements per Chip
    2
    Minimum Operating Supply Voltage
    4.5 V
    Latch Mode
    Transparent
    Number of Outputs per Chip
    16
    Bus Hold
    No
    Maximum Low Level Output Current
    48 mA
    Mounting
    Surface Mount
    Max Processing Temp
    260
    Maximum Operating Supply Voltage
    5.5 V
    Propagation Delay Test Condition
    50 pF
    Number of Input Enables per Element
    1
    Number of Output Enables per Element
    1
    Set/Reset
    No
    Number of Channels per Chip
    16
    Screening Level
    Military

    ECCN / UNSPSC

    Description
    Value
    ECCN:
    EAR99
    SCHEDULE B:
    8542310000
    UNSPSC:
    32101600
    UNSPSC VERSION:
    V15.1101

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