SN74LVC2G241DCUT by Texas Instruments | Buffers & Line Drivers | Avnet ASIA
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SN74LVC2G241DCUT

Texas Instruments

Buffer/Line Driver 2-CH Non-Inverting 3-ST CMOS 8-Pin VSSOP T/R

Manufacturer Part #: SN74LVC2G241DCUT

Alternate Part #: SN74LVC2G241DCUT


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Descriptions

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Information

This dual buffer/line driver is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC2G241 device is designed specifically to improve both the performance and density of 3-state memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

The SN74LVC2G241 device is organized as two 1-bit line drivers with separate output-enable (1OE, 2OE) inputs. When 1OE is low and 2OE is high, the device passes data from the A inputs to the Y outputs. When 1OE is high and 2OE is low, the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor, and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking or the current-sourcing capability of the driver.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Key Features

  • Available in the Texas Instruments NanoFree Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Max tpd of 4.1 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce)
    <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot)
    >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Can Be Used as a Down Translator to Translate Inputs From a Max of 5.5 V Down to the VCC Level
  • Latch-Up Performance Exceeds 100 mA Per
    JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Technical Attributes

    Description
    Value
    Find similar Parts
    Number of Outputs per Chip
    2
    Bus Hold
    No
    Number of Elements per Chip
    2
    Operating Temperature
    -40 to 85 °C
    Maximum Propagation Delay Time @ Maximum CL
    4.3@3.3V|3.7@5V ns
    Maximum High Level Output Current
    -32 mA
    Logic Function
    Buffer/Line Driver
    Maximum Low Level Output Current
    32 mA
    Supplier Package
    VSSOP
    Output Type
    3-State
    Propagation Delay Test Condition
    50 pF
    Number of Inputs per Chip
    2
    Pin Count
    8
    Product Dimensions
    2.3 x 2 x 0.85 mm
    Typical Operating Supply Voltage
    1.8|2.5|3.3|5 V
    Max Processing Temp
    260
    Lead Finish
    Gold
    Tolerant I/Os
    5 V
    Minimum Operating Supply Voltage
    1.65 V
    Maximum Operating Supply Voltage
    5.5 V
    Maximum Quiescent Current
    10 uA
    Polarity
    Non-Inverting
    Mounting
    Surface Mount
    MSL Level
    1
    Number of Channels per Chip
    2
    Input Signal Type
    Single-Ended
    Fabrication Technology
    CMOS
    Number of Output Enables per Chip
    1Low/1High

    ECCN / UNSPSC

    Description
    Value
    ECCN:
    EAR99
    SCHEDULE B:
    8542310000
    HTSN:
    8542310000
    UNSPSC:
    32101600
    UNSPSC VERSION:
    V15.1101

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