DS90CF388VJD/NOPB by Texas Instruments | LVDS | Avnet ASIA

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DS90CF388VJD/NOPB

Texas Instruments

LVDS Flat Panel Display 0.45V 100-Pin TQFP Tray

Manufacturer Part #: DS90CF388VJD/NOPB

Alternate Part #: DS90CF388VJD/NOPB


legend RoHS Compliant

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Information

The DS90C387/DS90CF388 transmitter/receiver pair is designed to support dual pixel data transmission between Host and Flat Panel Display up to QXGA resolutions. The transmitter converts 48 bits (Dual Pixel 24-bit color) of CMOS/TTL data into 8 LVDS (Low Voltage Differential Signalling) data streams. Control signals (VSYNC, HSYNC, DE and two user-defined signals) are sent during blanking intervals. At a maximum dual pixel rate of 112MHz, LVDS data line speed is 672Mbps, providing a total throughput of 5.38Gbps (672 Megabytes per second). Two other modes are also supported. 24-bit color data (single pixel) can be clocked into the transmitter at a maximum rate of 170MHz. In this mode, the transmitter provides single-to-dual pixel conversion, and the output LVDS clock rate is 85MHz maximum. The third mode provides inter-operability with FPD-Link devices.

The LDI chipset is improved over prior generations of FPD-Link devices and offers higher bandwidth support and longer cable drive with three areas of enhancement. To increase bandwidth, the maximum pixel clock rate is increased to 112 (170) MHz and 8 serialized LVDS outputs are provided. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects. DC balancing on a cycle-to-cycle basis, is also provided to reduce ISI (Inter-Symbol Interference). With pre-emphasis and DC balancing, a low distortion eye-pattern is provided at the receiver end of the cable. A cable deskew capability has been added to deskew long cables of pair-to-pair skew of up to +/−1 LVDS data bit time (up to 80 MHz Clock Rate). These three enhancements allow cables 5+ meters in length to be driven. This chipset is an ideal means to solve EMI and cable size problems for high-resolution flat panel applications. It provides a reliable interface based on LVDS technology that delivers the bandwidth needed for high-resolution panels while maximizing bit times, and keeping clock rates low to reduce EMI and shielding requirements.

Key Features

  • Complies with OpenLDI Specification for Digital Display Interfaces
  • 32.5 to 112/170MHz Clock Support for DS90C387, 40 to 112MHz Clock Support for DS90CF388
  • Supports SVGA through QXGA Panel Resolutions
  • Drives Long, Low Cost Cables
  • Up to 5.38Gbps Bandwidth
  • Pre-Emphasis Reduces Cable Loading Effects
  • DC Balance Data Transmission Provided by Transmitter Reduces ISI Distortion
  • Cable Deskew of +/−1 LVDS Data Bit Time (up to 80 MHz Clock Rate) of Pair-to-Pair Skew at Receiver Inputs; Intra-Pair Skew Tolerance of 300ps
  • Dual Pixel Architecture Supports Interface to GUI and Timing Controller; Optional Single Pixel Transmitter Inputs Support Single Pixel GUI Interface
  • Transmitter Rejects Cycle-to-Cycle Jitter
  • 5V Tolerant on Data and Control Input Pins
  • Programmable Transmitter Data and Control Strobe Select (Rising or Falling Edge Strobe)
  • Backward Compatible Configuration Select with FPD-Link
  • Optional Second LVDS Clock for Backward Compatibility w/ FPD-Link
  • Support for Two Additional User-Defined Control Signals in DC Balanced Mode
  • Compatible with ANSI/TIA/EIA-644-1995 LVDS Standard
  • Technical Attributes

    Description
    Value
    Find similar Parts
    Maximum Power Dissipation
    2800 mW
    Number of Drivers
    48
    Number of Elements per Chip
    8
    Minimum Operating Supply Voltage
    3 V
    Max Processing Temp
    260
    Supplier Package
    TQFP
    Maximum Operating Supply Voltage
    3.6 V
    Transmission Data Rate
    5380 Mbps
    Lead Finish
    Matte Tin
    Operating Temperature
    -10 to 70 °C
    Maximum Input Current
    15 uA
    Mounting
    Surface Mount
    Differential Input High Threshold Voltage
    0.1 V
    Number of Receivers
    8
    Typical Operating Supply Voltage
    3.3 V
    Input Type
    LVDS
    Product Dimensions
    14 x 14 x 1 mm
    MSL Level
    3
    Pin Count
    100
    Output Type
    Flat Panel Display
    Maximum Differential Output Voltage
    0.45 V
    Differential Input Low Threshold Voltage
    -0.1 V

    ECCN / UNSPSC

    Description
    Value
    ECCN:
    EAR99
    SCHEDULE B:
    8542390000"
    UNSPSC:
    32101600
    UNSPSC VERSION:
    V15.1101

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