MC74LCX573DTR2G by ON Semiconductor | Latches | Avnet ASIA
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MC74LCX573DTR2G

ON Semiconductor

Latch Transparent 3-ST 8-CH D-Type 20-Pin TSSOP T/R

Manufacturer Part #: MC74LCX573DTR2G

Alternate Part #: MC74LCX573DTR2G


RoHS Compliant

Descriptions

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Information

The MC74LCX573 is a high performance, non-inverting octal transparent latch operating from a 2.3 to 3.6V supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A V specification of 5.5V allows MC74LCX573 inputs to be safely driven from 5V devices.The MC74LCX573 contains 8 D-type latches with 3-state standard outputs. When the Latch Enable (LE) input is HGH, data on the Dn inputs enters the latches. n this condition, the latches are transparent, i.e., a latch output will change state each time its D input changes. When LE is LOW, the latches store the information that was present on the D inputs a setup time preceding the HGH-to-LOW transition of LE. The 3-state standard outputs are controlled by the Output Enable (OEbar) input. When OEbar is LOW, the standard outputs are enabled. When OEbar is HGH, the standard outputs are in the high impedance state, but this does not interfere with new data entering into the latches. The LCX573 flow through design facilitates easy PC board layout.

Key Features

  • Designed for 2.3 to 3.6V VCC Operation
  • 5V Tolerant - Interface Capability With 5V TTL Logic
  • Supports Live Insertion and Withdrawal
  • IOFF Specification Guarantees High Impedance When VCC = 0V
  • LVTTL Compatible
  • LVCMOS Compatible
  • 24mA Balanced Output Sink and Source Capability
  • Near Zero Static Supply Current in All Three Logic States (10mA) Substantially Reduces System Power Requirements
  • Latchup Performance Exceeds 500mA
  • ESD Performance: Human Body Model >2000V; Machine Model >200V
  • Pb-Free Packages are Available*

Technical Attributes

Description
Value
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Operating Temperature
-55 to 125 °C
Mounting
Surface Mount
Propagation Delay Test Condition
50 pF
Set/Reset
No
Output Type
3-State
Number of Inputs per Chip
8
Latch Mode
Transparent
Number of Output Enables per Element
1
Maximum Propagation Delay Time @ Maximum CL
9@2.7V|8@3.3V ns
Typical Operating Supply Voltage
2.5|3.3 V
Pin Count
20
Maximum High Level Output Current
-24 mA
Number of Outputs per Chip
8
Maximum Low Level Output Current
24 mA
Max Processing Temp
260
Supplier Package
TSSOP
Type
D-Type
Number of Channels per Chip
8
Product Dimensions
6.6 x 4.5 x 1.05 mm
Maximum Quiescent Current
10 uA
Polarity
Non-Inverting
Fabrication Technology
CMOS
Bus Hold
No
Lead Finish
Gold
Tolerant I/Os
5 V
Maximum Operating Supply Voltage
3.6 V
Minimum Operating Supply Voltage
2 V
MSL Level
1
Number of Elements per Chip
1
Number of Input Enables per Element
1

ECCN / UNSPSC

Description
Value
ECCN:
EAR99
SCHEDULE B:
85423900228.1
HTSN:
85423900228.1
UNSPSC:
32101600
UNSPSC VERSION:
V15.1101
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