MC74HC595ADR2G by ON Semiconductor | Counter Shift Register | Avnet ASIA
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MC74HC595ADR2G

ON Semiconductor

Shift Register Single 8-Bit Serial to Serial/Parallel 16-Pin SOIC T/R

Manufacturer Part #: MC74HC595ADR2G

Alternate Part #: MC74HC595ADR2G


legend RoHS Compliant

Descriptions

Documents

Subs/Alternatives

Information

The MC74HC595A consists of an 8-bit shift register and an 8-bit D-type latch with three-state parallel outputs. The shift register accepts serial data and provides a serial output. The shift register also provides parallel data to the 8-bit latch. The shift register and latch have independent clock inputs. This device also has an asynchronous reset for the shift register. The HC595A directly interfaces with the SPI serial data port on CMOS MPUs and MCUs.

Key Features

  • Output Drive Capability: 15 LSTTL Loads
  • Outputs Directly Interface to CMOS, NMOS, and TTL
  • Operating Voltage Range: 2.0 to 6.0 V
  • Low Input Current: 1.0 µA
  • High Noise Immunity Characteristic of CMOS Devices
  • In Compliance with the Requirements Defined by JEDEC Standard No. 7A
  • Chip Complexity: 328 FETs or 82 Equivalent Gates
  • Improvements over HC595
    Improved Propagation Delays
    50% Lower Quiescent Power
    Improved Input Noise and Latchup Immunity
  • These Devices are Pb−Free, Halogen Free and are RoHS Compliant

Technical Attributes

Description
Value
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Operating Temperature
-55 to 125 °C
Mounting
Surface Mount
Reset Type
Asynchronous
Typical Operating Supply Voltage
2.5|3.3|5 V
Direction Type
Uni-Directional
Maximum Quiescent Current
0.004 mA
Propagation Delay Test Condition
50 pF
Logic Function
Shift Register
Parallel Enable Input
No
Terminal Count Output
No
Number of Stages
8
Supplier Package
SOIC
Output Type
3-State
Pin Count
16
Operation Mode
Serial to Serial/Parallel
Number of Element Outputs
9
Triggering Type
Positive-Edge
Maximum Propagation Delay Time @ Maximum CL
140@2V|100@3V|28@4.5V|24@6V ns
Maximum Operating Supply Voltage
6 V
Minimum Operating Supply Voltage
2 V
Number of Elements per Chip
1
Fabrication Technology
CMOS
Number of Element Inputs
1
MSL Level
1
Lead Finish
Matte Tin
Product Dimensions
10 x 4 x 1.5 mm
Max Processing Temp
260

ECCN / UNSPSC

Description
Value
ECCN:
EAR99
SCHEDULE B:
85423900228.1
HTSN:
85423900228.1
UNSPSC:
32101635
UNSPSC VERSION:
V15.1101
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