The PCA9698 provides 40-bit parallel input/output (I/O) port expansion for I²C-bus applications organized in 5 banks of 8 I/Os. At 5 V supply voltage, the outputs are capable of sourcing 10 mA and sinking 25 mA with a total package load of 1 A to allow direct driving of 40 LEDs. Any of the 40 I/O ports can be configured as an input or output. The PCA9698 is the first GPIO device in a new Fast-mode Plus (Fm+) family. Fm+ devices offer higher frequency (up to 1 MHz) and longer, more densely populated bus operation (up to 4000 pF). The device is fully configurable: output ports can be programmed to be totem-pole or open-drain and logic states can change at either the Acknowledge (bank change) or the Stop Command (global change), each input port can be masked to prevent it from generating interrupts when its state changes, I/O data logic state can be inverted when read by the system master. An open-drain interrupt output pin (INT) allows monitoring of the input pins and is asserted each time a change occurs in one or several input ports (unless masked). The Output Enable pin (OE) 3-states any I/O selected as output and can be used as an input signal to blink or dim LEDs (PWM with frequency > 80 Hz and change duty cycle). A 'GPIO All Call' command allows to program multiple Advanced GPIOs at the same time even if they have different I²C-bus addresses. This allows optimal code programming when more than one device needs to be programmed with the same instruction or if all outputs need to be turned on or off at the same time (for example, LED test). The Device ID, hard coded in the PCA9698, allows the system master to read manufacturer, part type and revision information. The SMBus Alert feature allows the SMBALERT\ pins of multiple devices with this feature to be connected together to form a wired-AND signal and to be used in conjunction with the SMBus Alert Response Address. The internal Power-On Reset (POR) or hardware reset pin (RESET\) initializes the 40 I/Os as inputs. Three address select pins configure one of 64 slave addresses. The PCA9698 is available in 56-pin TSSOP and HVQFN packages and is specified over the -40 Cel to +85 Cel industrial temperature range.
1 MHz Fast-mode Plus I²C-bus serial interface
Compliant with I²C-bus Fast-mode (400 kHz) and Standard-mode (100 kHz)
2.3 V to 5.5 V operation with 5.5 V tolerant I/Os
40 configurable I/O pins that default to inputs at power-up
Programmable totem-pole (10 mA source, 25 mA sink) or open-drain (25 mA sink) with controlled edge rate output structure. Default to totem-pole on power-up.
Active LOW Output Enable (OE) input pin 3-states all outputs. Polarity can be programmed to active HIGH through the I²C-bus. Defaults to OE on power-up.
Output state change programmable on the Acknowledge or the STOP Command to update outputs byte-by-byte or all at the same time respectively. Defaults to Acknowledge on power-up.
Open-drain active LOW Interrupt (INT) output pin allows monitoring of logic level change of pins programmed as inputs
Programmable Interrupt Mask Control for input pins that do not require an interrupt when their states change
Polarity Inverter register allows inversion of the polarity of the I/O pins when read
Active LOW SMBus Alert (SMBALERT) output pin allows to initiate SMBus 'Alert Response Address' sequence. Own slave address sent when sequence initiated.
Active LOW Reset (RESET) input pin resets device to power-up default state
GPIO All Call address allows programming of more than one device at the same time with the same parameters
64 programmable slave addresses using 3 address pins
Readable Device ID (manufacturer, device type and revision)
Designed for live insertion in PICMG applications
Minimize line disturbance (IOFF and power-up 3-state)
Signal transient rejection (50 ns noise filter and robust I²C-bus state machine)
Low standby current
-40 Cel to +85 Cel operation
ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA