AS7C34098A-15TCN by Alliance Memory | SRAM Chip | Avnet ASIA
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AS7C34098A-15TCN

Alliance Memory

SRAM Chip Async Single 3.3V 4M-Bit 256K x 16 15ns 44-Pin TSOP-II

Manufacturer Part #: AS7C34098A-15TCN

Alternate Part #: AS7C34098A-15TCN


legend RoHS Compliant

Descriptions

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Information

The AS7C34098A is a high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 262,144 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired.Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE ) of 4/5/6/7 ns are ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank memory systems.When CE is high the device enters standby mode. The device is guaranteed not to exceed 28.8mW power consumption in CMOS standby mode. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1–I/O16 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode.The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.All chip inputs and outputs are TTL- and CMOS-compatible, and operation is for 3.3V (AS7C34098A) supply. The device is available in the JEDEC standard 400-mil, 44-pin SOJ, TSOP 2.

Key Features

  • Industrial and commercial temperature
  • Organization: 262,144 words × 16 bits
  • Center power and ground pins
  • High speed
    • 10/12/15/20 ns address access time
    • 4/5/6/7 ns output enable access time
  • Low power consumption: ACTIVE
    • 650 mW /max @ 10 ns
  • Low power consumption: STANDBY
    • 28.8 mW /max CMOS
  • Individual byte read/write controls
  • Easy memory expansion with CE, OE inputs
  • TTL- and CMOS-compatible, three-state I/O
  • JEDEC standard packages
    • 44-pin SOJ -400-mil
    • 44-pin TSOP 2
    • 48-pin Mini BGA
  • ESD protection ≥ 2000 volts
  • Latch-up current ≥ 200 mA

Technical Attributes

Description
Value
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Mounting
Surface Mount
Timing Type
Asynchronous
Screening Level
Commercial
Minimum Operating Supply Voltage
3 V
Maximum Operating Supply Voltage
3.6 V
Pin Count
44
Number of Bits per Word
16 Bit
Number of Words
256 kWords
Number of I/O Lines
16 Bit
Maximum Random Access Time
15 ns
Density
4 Mb
Address Bus Width
18 Bit
Supplier Package
TSOP-II
Typical Operating Supply Voltage
3.3 V
Maximum Operating Current
130 mA
Product Dimensions
18.54 x 10.29 x 1.05 mm
Number of Ports
1

ECCN / UNSPSC

Description
Value
ECCN:
3A991.b.2.a
SCHEDULE B:
8542320040"
HTSN:
8542320040"
UNSPSC:
32101603
UNSPSC VERSION:
V15.1101
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