AS7C1026B-12TCN by Alliance Memory | SRAM ICs | Avnet ASIA
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AS7C1026B-12TCN

Alliance Memory

SRAM Chip Async Single 5V 1M-Bit 64K x 16 12ns 44-Pin TSOP-II

Manufacturer Part #: AS7C1026B-12TCN

Avnet Manufacturer Part #: AS7C1026B-12TCN


RoHS Compliant

Descriptions

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Information

The AS7C1026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high-performance applications.

Key Features

  • Industrial and commercial versions
  • Organization: 65,536 words × 16 bits
  • Center power and ground pins for low noise
  • High speed
    • 10/12/15/20 ns address access time
    • 5, 6, 7, 8 ns output enable access time
  • Low power consumption: ACTIVE
    • 605 mW / max @ 10 ns
  • Low power consumption: STANDBY
    • 55 mW / max CMOS I/O
  • 6 T 0.18 u CMOS technology
  • Easy memory expansion with CE, OE inputs
  • TTL-compatible, three-state I/O
  • JEDEC standard packaging
    • 44-pin 400 mil SOJ
    • 44-pin TSOP 2-400
  • ESD protection ≥ 2000 volts
  • Latch-up current ≥ 200 mA

Technical Attributes

Description
Value
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Maximum Operating Current
100 mA
Pin Count
44
Number of Words
64 kWords
Maximum Operating Supply Voltage
5.5 V
Product Dimensions
18.42 x 10.16 x 1 mm
Number of Ports
1
Number of I/O Lines
16 Bit
Mounting
Surface Mount
Address Bus Width
16 Bit
Number of Bits per Word
16 Bit
Operating Temperature
0 to 70 °C
Timing Type
Asynchronous
Maximum Random Access Time
12 ns
Typical Operating Supply Voltage
5 V
Minimum Operating Supply Voltage
4.5 V
Supplier Package
TSOP-II
Density
1 Mb
Screening Level
Commercial

ECCN / UNSPSC

Description
Value
ECCN:
EAR99
SCHEDULE B:
8542320040
HTSN:
8542320040
UNSPSC:
32101603
UNSPSC VERSION:
V15.1101
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