74LCX74MX by Fairchild Semiconductor | | Avnet ASIA
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74LCX74MX

Fairchild Semiconductor

Flip Flop D-Type Pos-Edge 2-Element 14-Pin SOIC N T/R

Manufacturer Part #: 74LCX74MX

Alternate Part #: 74LCX74MX


legend RoHS Compliant

Descriptions

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Information

The 74LCX74 is a Low Voltage Dual D-Type Positive Edge-Triggered Flip-Flop with 5V Tolerant Inputs The LCX74 is a dual D-type flip-flop with Asynchronous Clear and Set inputs and complementary (Q, Q#) outputs. Information at the input is transferred to the outputs on the positive edge of the clock pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be transferred to the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs: LOW input to S#D (Set) sets Q to HIGH level LOW input to C#D (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on C#D and S#D makes both Q and Q# HIGH

Key Features

  • 5V tolerant inputs
  • 2.3V-3.6V VCC specifications provided
  • 7.0 ns tPD max (VCC = 3.3V), 10 µA ICC max
  • Power down high impedance inputs and outputs
  • ±24 mA output drive (VCC = 3.0V)
  • Implements patented noise/EMI reduction circuitry
  • Latch-up performance exceeds JEDEC 78 conditions
  • ESD performance: Human body model > 2000V Machine model > 200V
  • Leadless Pb-Free DQFN package

Technical Attributes

Description
Value
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Maximum Operating Supply Voltage
3.6 V
Bus Hold
No
Number of Element Outputs
1
Triggering Type
Positive-Edge
Maximum Low Level Output Current
24 mA
Mounting
Surface Mount
Minimum Operating Supply Voltage
2 V
Input Signal Type
Single-Ended
Fabrication Technology
CMOS
Output Signal Type
Differential
Number of Elements per Chip
2
Polarity
Inverting/Non-Inverting
Maximum Quiescent Current
0.01 mA
Logic Function
D-Type
Propagation Delay Test Condition
50 pF
Number of Element Inputs
1
Number of Channels per Chip
2
Typical Operating Supply Voltage
2.5|3.3 V
Set/Reset
Set/Reset
Maximum High Level Output Current
-24 mA
Operating Temperature
-40 to 85 °C
Maximum Propagation Delay Time @ Maximum CL
8@2.7V|7@3.3V ns
Max Processing Temp
260
Lead Finish
Matte Tin

ECCN / UNSPSC

Description
Value
ECCN:
EAR99
SCHEDULE B:
8542390000
HTSN:
8542390000
UNSPSC:
32101634
UNSPSC VERSION:
V15.1101

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