Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
date_generatedMon Feb 03 09:17:07 2014 product_versionVivado v2013.3 (64-bit)
build_version329390 os_platformWIN64
registration_id210654419_1777487065_0_472 tool_flowVivado
betaFALSE route_designTRUE
target_familyzynq target_devicexc7z010
target_packageclg400 target_speed-1
random_id5661eec9a5dd5596aaef4fcfd279f7f4 project_id78ef5be7ea6b4364ab1d8a8c0bc7f399
project_iteration1

user_environment
os_nameMicrosoft Windows 7 , 64-bit os_releaseService Pack 1 (build 7601)
cpu_nameIntel(R) Core(TM) i7-2600 CPU @ 3.40GHz cpu_speed3392 MHz
total_processors1 system_ram17.000 GB

vivado_usage
project_data
srcsetcount=2 constraintsetcount=1 designmode=RTL prproject=false
reconfigpartitioncount=0 reconfigmodulecount=0 hdproject=false partitioncount=0
synthesisstrategy=Vivado Synthesis Defaults implstrategy=Vivado Implementation Defaults currentsynthesisrun=synth_1 currentimplrun=impl_1
totalsynthesisruns=1 totalimplruns=1 board=MicroZed Board
other_data
guimode=1

unisim_transformation
pre_unisim_transformation
bibuf=130 bufg=1 gnd=4 iobuf=6
lut1=31 ps7=1
post_unisim_transformation
bibuf=130 bufg=1 gnd=4 ibuf=6
lut1=31 obuft=6 ps7=1

placer
usage
lut=6 ff=0 bram36=0 dsp=0
iob=6 bufg=0 global_clocks=0 pll=0
bufr=0 nets=302 movable_instances=153 pins=3611
bogomips=0 effort=2 threads=2 placer_timing_driven=1
timing_constraints_exist=1 placer_runtime=0.907000

ip_statistics
IP_Integrator/1
iptotal=1 x_ipvendor=xilinx.com x_iplanguage=VERILOG numblks=1
numreposblks=1 numnonxlnxblks=0 numhierblks=0 maxhierdepth=0
da_ps7_cnt=1
processing_system7_v5_3_processing_system7/1
iptotal=1 x_ipproduct=Vivado 2013.3 x_ipvendor=xilinx.com x_iplibrary=ip
x_ipname=processing_system7 x_ipversion=5.3 x_ipcorerevision=0 x_iplanguage=VERILOG
c_en_emio_enet0=0 c_en_emio_enet1=0 c_en_emio_trace=0 c_include_trace_buffer=0
c_trace_buffer_fifo_size=128 use_trace_data_edge_detector=0 c_trace_buffer_clock_delay=12 c_emio_gpio_width=6
c_include_acp_trans_check=0 c_use_default_acp_user_val=0 c_s_axi_acp_aruser_val=31 c_s_axi_acp_awuser_val=31
c_m_axi_gp0_id_width=12 c_m_axi_gp0_enable_static_remap=0 c_m_axi_gp1_id_width=12 c_m_axi_gp1_enable_static_remap=0
c_s_axi_gp0_id_width=6 c_s_axi_gp1_id_width=6 c_s_axi_acp_id_width=3 c_s_axi_hp0_id_width=6
c_s_axi_hp0_data_width=64 c_s_axi_hp1_id_width=6 c_s_axi_hp1_data_width=64 c_s_axi_hp2_id_width=6
c_s_axi_hp2_data_width=64 c_s_axi_hp3_id_width=6 c_s_axi_hp3_data_width=64 c_m_axi_gp0_thread_id_width=12
c_m_axi_gp1_thread_id_width=12 c_num_f2p_intr_inputs=1 c_dq_width=32 c_dqs_width=4
c_dm_width=4 c_mio_primitive=54 c_ps7_si_rev=PRODUCTION c_fclk_clk0_buf=true
c_fclk_clk1_buf=false c_fclk_clk2_buf=false c_fclk_clk3_buf=false c_package_name=clg400

report_power
command_line_options
-verbose=default::[not_specified] -hier=default::power -no_propagation=default::[not_specified] -format=default::text
-file=[specified] -name=default::[not_specified] -xpe=default::[not_specified] -return_string=default::[not_specified]
-vid=default::[not_specified] -append=default::[not_specified] -l=default::[not_specified]
usage
customer=TBD customer_class=TBD flow_state=routed family=zynq
die=xc7z010clg400-1 package=clg400 speedgrade=-1 version=2013.3
platform=nt64 temp_grade=commercial process=typical simulation_file=None
netlist_net_matched=NA pct_clock_constrained=0 pct_inputs_defined=0 user_junc_temp=41.5 (C)
ambient_temp=25.0 (C) user_effective_thetaja=11.533192 airflow=250 (LFM) heatsink=none
user_thetasa=0.0 (C/W) board_selection=medium (10"x10") board_layers=8to11 (8 to 11 Layers) user_thetajb=9.3 (C/W)
user_board_temp=25.0 (C) junction_temp=41.5 (C) input_toggle=12.500000 output_toggle=12.500000
bi-dir_toggle=12.500000 output_enable=1.000000 bidir_output_enable=1.000000 output_load=5.000000
ff_toggle=12.500000 ram_enable=50.000000 ram_write=50.000000 dsp_output_toggle=12.500000
set/reset_probability=0.000000 enable_probability=0.990000 on-chip_power=1.432127 dynamic=1.308968
effective_thetaja=11.5 thetasa=0.0 (C/W) thetajb=9.3 (C/W) off-chip_power=0.120750
logic=0.000005 signals=0.000168 i/o=0.001449 ps7=1.307346
devstatic=0.123159 vccint_voltage=1.000000 vccint_total_current=0.006501 vccint_dynamic_current=0.000198
vccint_static_current=0.006304 vccaux_voltage=1.800000 vccaux_total_current=0.011669 vccaux_dynamic_current=0.000117
vccaux_static_current=0.011552 vcco33_voltage=3.300000 vcco33_total_current=0.000000 vcco33_dynamic_current=0.000000
vcco33_static_current=0.000000 vcco25_voltage=2.500000 vcco25_total_current=0.000000 vcco25_dynamic_current=0.000000
vcco25_static_current=0.000000 vcco18_voltage=1.800000 vcco18_total_current=0.001675 vcco18_dynamic_current=0.000675
vcco18_static_current=0.001000 vcco15_voltage=1.500000 vcco15_total_current=0.000000 vcco15_dynamic_current=0.000000
vcco15_static_current=0.000000 vcco135_voltage=1.350000 vcco135_total_current=0.000000 vcco135_dynamic_current=0.000000
vcco135_static_current=0.000000 vcco12_voltage=1.200000 vcco12_total_current=0.000000 vcco12_dynamic_current=0.000000
vcco12_static_current=0.000000 vccaux_io_voltage=1.800000 vccaux_io_total_current=0.000000 vccaux_io_dynamic_current=0.000000
vccaux_io_static_current=0.000000 vccbram_voltage=1.000000 vccbram_total_current=0.000387 vccbram_dynamic_current=0.000000
vccbram_static_current=0.000387 mgtavcc_voltage=1.000000 mgtavcc_total_current=0.000000 mgtavcc_dynamic_current=0.000000
mgtavcc_static_current=0.000000 mgtavtt_voltage=1.200000 mgtavtt_total_current=0.000000 mgtavtt_dynamic_current=0.000000
mgtavtt_static_current=0.000000 mgtvccaux_voltage=1.800000 mgtvccaux_total_current=0.000000 mgtvccaux_dynamic_current=0.000000
mgtvccaux_static_current=0.000000 vccpint_voltage=1.000000 vccpint_total_current=0.418133 vccpint_dynamic_current=0.390853
vccpint_static_current=0.027280 vccpaux_voltage=1.800000 vccpaux_total_current=0.044680 vccpaux_dynamic_current=0.034350
vccpaux_static_current=0.010330 vccpll_voltage=1.800000 vccpll_total_current=0.116000 vccpll_dynamic_current=0.113000
vccpll_static_current=0.003000 vcco_ddr_voltage=1.500000 vcco_ddr_total_current=0.510750 vcco_ddr_dynamic_current=0.508750
vcco_ddr_static_current=0.002000 vcco_mio0_voltage=1.800000 vcco_mio0_total_current=0.003750 vcco_mio0_dynamic_current=0.002750
vcco_mio0_static_current=0.001000 vcco_mio1_voltage=1.800000 vcco_mio1_total_current=0.003187 vcco_mio1_dynamic_current=0.002187
vcco_mio1_static_current=0.001000 vccadc_voltage=1.800000 vccadc_total_current=0.020000 vccadc_dynamic_current=0.000000
vccadc_static_current=0.020000 confidence_level_design_state=High confidence_level_clock_activity=Low confidence_level_io_activity=Low
confidence_level_internal_activity=Medium confidence_level_device_models=High confidence_level_overall=Low

report_utilization
slice_logic
slice_luts_used=6 slice_luts_loced=0 slice_luts_available=17600 slice_luts_util_percentage=0.03
lut_as_logic_used=6 lut_as_logic_loced=0 lut_as_logic_available=17600 lut_as_logic_util_percentage=0.03
lut_as_memory_used=0 lut_as_memory_loced=0 lut_as_memory_available=6000 lut_as_memory_util_percentage=0.00
slice_registers_used=0 slice_registers_loced=0 slice_registers_available=35200 slice_registers_util_percentage=0.00
register_as_flip_flop_used=0 register_as_flip_flop_loced=0 register_as_flip_flop_available=35200 register_as_flip_flop_util_percentage=0.00
register_as_latch_used=0 register_as_latch_loced=0 register_as_latch_available=35200 register_as_latch_util_percentage=0.00
f7_muxes_used=0 f7_muxes_loced=0 f7_muxes_available=8800 f7_muxes_util_percentage=0.00
f8_muxes_used=0 f8_muxes_loced=0 f8_muxes_available=4400 f8_muxes_util_percentage=0.00
slice_used=4 slice_loced=0 slice_available=4400 slice_util_percentage=0.09
lut_as_logic_used=6 lut_as_logic_loced=0 lut_as_logic_available=17600 lut_as_logic_util_percentage=0.03
using_o5_output_only_used=0 using_o5_output_only_loced= using_o6_output_only_used=6 using_o6_output_only_loced=
using_o5_and_o6_used=0 using_o5_and_o6_loced= lut_as_memory_used=0 lut_as_memory_loced=0
lut_as_memory_available=6000 lut_as_memory_util_percentage=0.00 lut_as_distributed_ram_used=0 lut_as_distributed_ram_loced=0
lut_as_shift_register_used=0 lut_as_shift_register_loced=0 lut_flip_flop_pairs_used=6 lut_flip_flop_pairs_loced=0
lut_flip_flop_pairs_available=17600 lut_flip_flop_pairs_util_percentage=0.03 fully_used_lut_ff_pairs_used=0 fully_used_lut_ff_pairs_loced=
lut_ff_pairs_with_unused_lut_used=0 lut_ff_pairs_with_unused_lut_loced= lut_ff_pairs_with_unused_flip_flop_used=6 lut_ff_pairs_with_unused_flip_flop_loced=
unique_control_sets_used=0 minimum_number_of_registers_lost_to_control_set_restriction_used=0(Lost)
memory
block_ram_tile_used=0 block_ram_tile_loced=0 block_ram_tile_available=60 block_ram_tile_util_percentage=0.00
ramb36_fifo*_used=0 ramb36_fifo*_loced=0 ramb36_fifo*_available=60 ramb36_fifo*_util_percentage=0.00
ramb18_used=0 ramb18_loced=0 ramb18_available=120 ramb18_util_percentage=0.00
dsp
dsps_used=0 dsps_loced=0 dsps_available=80 dsps_util_percentage=0.00
io_and_gtx
bonded_iob_used=6 bonded_iob_loced=6 bonded_iob_available=100 bonded_iob_util_percentage=6.00
iob_master_pads_used=2 iob_master_pads_loced= iob_slave_pads_used=3 iob_slave_pads_loced=
bonded_ipads_used=0 bonded_ipads_loced=0 bonded_ipads_available=2 bonded_ipads_util_percentage=0.00
bonded_iopads_used=0 bonded_iopads_loced=0 bonded_iopads_available=130 bonded_iopads_util_percentage=0.00
ibufgds_used=0 ibufgds_loced=0 ibufgds_available=96 ibufgds_util_percentage=0.00
idelayctrl_used=0 idelayctrl_loced=0 idelayctrl_available=2 idelayctrl_util_percentage=0.00
in_fifo_used=0 in_fifo_loced=0 in_fifo_available=8 in_fifo_util_percentage=0.00
out_fifo_used=0 out_fifo_loced=0 out_fifo_available=8 out_fifo_util_percentage=0.00
phaser_ref_used=0 phaser_ref_loced=0 phaser_ref_available=2 phaser_ref_util_percentage=0.00
phy_control_used=0 phy_control_loced=0 phy_control_available=2 phy_control_util_percentage=0.00
phaser_out_phaser_out_phy_used=0 phaser_out_phaser_out_phy_loced=0 phaser_out_phaser_out_phy_available=8 phaser_out_phaser_out_phy_util_percentage=0.00
phaser_in_phaser_in_phy_used=0 phaser_in_phaser_in_phy_loced=0 phaser_in_phaser_in_phy_available=8 phaser_in_phaser_in_phy_util_percentage=0.00
idelaye2_idelaye2_finedelay_used=0 idelaye2_idelaye2_finedelay_loced=0 idelaye2_idelaye2_finedelay_available=100 idelaye2_idelaye2_finedelay_util_percentage=0.00
odelaye2_odelaye2_finedelay_used=0 odelaye2_odelaye2_finedelay_loced=0 odelaye2_odelaye2_finedelay_available=0 odelaye2_odelaye2_finedelay_util_percentage=0.00
ibufds_gte2_used=0 ibufds_gte2_loced=0 ibufds_gte2_available=0 ibufds_gte2_util_percentage=0.00
ilogic_used=0 ilogic_loced=0 ilogic_available=100 ilogic_util_percentage=0.00
ologic_used=0 ologic_loced=0 ologic_available=100 ologic_util_percentage=0.00
clocking
bufgctrl_used=0 bufgctrl_loced=0 bufgctrl_available=32 bufgctrl_util_percentage=0.00
bufio_used=0 bufio_loced=0 bufio_available=8 bufio_util_percentage=0.00
mmcme2_adv_used=0 mmcme2_adv_loced=0 mmcme2_adv_available=2 mmcme2_adv_util_percentage=0.00
plle2_adv_used=0 plle2_adv_loced=0 plle2_adv_available=2 plle2_adv_util_percentage=0.00
bufmrce_used=0 bufmrce_loced=0 bufmrce_available=4 bufmrce_util_percentage=0.00
bufhce_used=0 bufhce_loced=0 bufhce_available=48 bufhce_util_percentage=0.00
bufr_used=0 bufr_loced=0 bufr_available=8 bufr_util_percentage=0.00
specific_feature
bscane2_used=0 bscane2_loced=0 bscane2_available=4 bscane2_util_percentage=0.00
capturee2_used=0 capturee2_loced=0 capturee2_available=1 capturee2_util_percentage=0.00
dna_port_used=0 dna_port_loced=0 dna_port_available=1 dna_port_util_percentage=0.00
efuse_usr_used=0 efuse_usr_loced=0 efuse_usr_available=1 efuse_usr_util_percentage=0.00
frame_ecce2_used=0 frame_ecce2_loced=0 frame_ecce2_available=1 frame_ecce2_util_percentage=0.00
icape2_used=0 icape2_loced=0 icape2_available=2 icape2_util_percentage=0.00
startupe2_used=0 startupe2_loced=0 startupe2_available=1 startupe2_util_percentage=0.00
xadc_used=0 xadc_loced=0 xadc_available=1 xadc_util_percentage=0.00
primitives
bibuf_used=130 obuft_used=6 lut1_used=6 ibuf_used=6
ps7_used=1
io_standard
lvcmos12=0 lvcmos18=1 lvcmos33=1 diff_hsul_12=0
diff_sstl135_r=0 diff_sstl15_r=0 diff_sstl18_ii=0 diff_hstl_ii_18=0
diff_hstl_ii=0 sstl135_r=0 sstl15_r=0 sstl18_ii=0
ppds_25=0 tmds_33=0 hstl_ii_18=0 lvds_25=0
diff_mobile_ddr=0 pci33_3=0 hstl_i=0 hsul_12=0
lvcmos15=0 lvcmos25=0 lvttl=0 diff_sstl135=0
diff_sstl15=1 diff_sstl18_i=0 diff_hstl_i_18=0 diff_hstl_i=0
sstl135=0 sstl15=1 sstl18_i=0 mini_lvds_25=0
rsds_25=0 hstl_i_18=0 blvds_25=0 mobile_ddr=0
hstl_ii=0

router
usage
lut=6 ff=0 bram36=0 dsp=0
iob=6 bufg=0 global_clocks=0 pll=0
bufr=0 nets=302 movable_instances=153 pins=3611
bogomips=0 high_fanout_nets=1 effort=2 threads=2
router_timing_driven=1 timing_constraints_exist=1 congestion_level=0 router_runtime=11.259000

synthesis
command_line_options
-part=xc7z010clg400-1 -name=default::[not_specified] -top=design_1_wrapper -include_dirs=default::[not_specified]
-generic=default::[not_specified] -verilog_define=default::[not_specified] -constrset=default::[not_specified] -seu_protect=default::none
-flatten_hierarchy=default::rebuilt -gated_clock_conversion=default::off -directive=default::default -rtl=default::[not_specified]
-bufg=default::12 -fanout_limit=default::10000 -shreg_min_size=default::3 -mode=default::default
-fsm_extraction=default::auto -keep_equivalent_registers=default::[not_specified] -resource_sharing=default::auto -control_set_opt_threshold=default::4
usage
elapsed=00:00:28s memory_peak=759.281MB memory_gain=555.727MB