# ---------------------------------------------------------------------------- # # ** ** ** ** **** ** ********** ********** ® # ** ** ** ** ** ** ** ** ** # ** ** ** ** ** ** ** ** ** # ** ** ** ** ** ** ** ********* ** # ** ** ** ** ** ** ** ** ** # ** ** **** ** ** ** ** ** # ** ......... ** ** ** **** ********** ** # ........... # Reach Further™ # # ---------------------------------------------------------------------------- # # This design is the property of Avnet. Publication of this # design is not authorized without written consent from Avnet. # # Please direct any questions to the Avnet Technical Community: # http://community.avnet.com/ # # Product information is available at: # http://www.avnet.com # # Disclaimer: # Avnet, Inc. makes no warranty for the use of this code or design. # This code is provided "As Is". Avnet, Inc assumes no responsibility for # any errors, which may appear in this code, nor does it make a commitment # to update the information contained herein. Avnet, Inc specifically # disclaims any implied warranties of fitness for a particular purpose. # Copyright(c) 2017 Avnet, Inc. # All rights reserved. # # ---------------------------------------------------------------------------- # # Create Date: Oct 05, 2017 # Design Name: TSN with UltraZed and FMC-Network # Module Name: UltraZed_EG_PCIe_CC_Network_Master_XDC_File_v1.xdc # Project Name: UltraZed TSN Project # Target Devices: Xilinx Zynq Ultrascale+ 3EG # Hardware Boards: UltraZed-EG SOM, PCIe Carrier, FMC Network # # Tool versions: Xilinx Vivado # # Description: Constraints for UltraZed + FMC-Network # # Dependencies: # # Revision: Oct 05, 2017: 1.00 Initial version # Jun 11, 2018 1.01 Updated for Production FMC-Network # # ---------------------------------------------------------------------------- # FMC LPC Interface - FMC Network # set_property PACKAGE_PIN R4 [get_ports {M2C_125MHZ_N}]; # JX2_HP_DP_27_GC_N - FMC_CLK0_M2C_N set_property PACKAGE_PIN P4 [get_ports {M2C_125MHZ_P}]; # JX2_HP_DP_27_GC_P - FMC_CLK0_M2C_P set_property PACKAGE_PIN L3 [get_ports {ETH1_RX_EN}]; # JX1_HP_DP_37_GC_N - FMC_LA00_CC_N set_property PACKAGE_PIN M3 [get_ports {ETH1_RX_CLK}]; # JX1_HP_DP_37_GC_P - FMC_LA00_CC_P set_property PACKAGE_PIN N3 [get_ports {ETH2_RX_EN}]; # JX1_HP_DP_36_GC_N - FMC_LA01_CC_N set_property PACKAGE_PIN N4 [get_ports {ETH2_RX_CLK}]; # JX1_HP_DP_36_GC_P - FMC_LA01_CC_P set_property PACKAGE_PIN K2 [get_ports {ETH1_RX_D1}]; # JX1_HP_DP_41_N - FMC_LA02_N set_property PACKAGE_PIN L2 [get_ports {ETH1_RX_D0}]; # JX1_HP_DP_41_P - FMC_LA02_P set_property PACKAGE_PIN R1 [get_ports {ETH1_RX_D3}]; # JX1_HP_DP_39_N - FMC_LA03_N set_property PACKAGE_PIN R2 [get_ports {ETH1_RX_D2}]; # JX1_HP_DP_39_P - FMC_LA03_P set_property PACKAGE_PIN K5 [get_ports {ETH1_TX_CLK}]; # JX1_HP_DP_35_N - FMC_LA04_N set_property PACKAGE_PIN K6 [get_ports {ETH1_TX_D0}]; # JX1_HP_DP_35_P - FMC_LA04_P set_property PACKAGE_PIN M5 [get_ports {ETH1_RST_N}]; # JX1_HP_DP_38_N - FMC_LA05_N set_property PACKAGE_PIN N5 [get_ports {ETH1_MDC}]; # JX1_HP_DP_38_P - FMC_LA05_P set_property PACKAGE_PIN L5 [get_ports {ETH1_MDIO}]; # JX1_HP_DP_40_N - FMC_LA06_N set_property PACKAGE_PIN M6 [get_ports {ETH2_RX_D0}]; # JX1_HP_DP_40_P - FMC_LA06_P set_property PACKAGE_PIN V1 [get_ports {ETH1_TX_EN}]; # JX1_HP_DP_31_N - FMC_LA07_N set_property PACKAGE_PIN U1 [get_ports {ETH1_TX_D3}]; # JX1_HP_DP_31_P - FMC_LA07_P set_property PACKAGE_PIN J4 [get_ports {ETH1_TX_D2}]; # JX1_HP_DP_33_N - FMC_LA08_N set_property PACKAGE_PIN K4 [get_ports {ETH1_TX_D1}]; # JX1_HP_DP_33_P - FMC_LA08_P set_property PACKAGE_PIN J6 [get_ports {ETH2_RX_D3}]; # JX1_HP_DP_32_N - FMC_LA09_N set_property PACKAGE_PIN J7 [get_ports {ETH2_RX_D1}]; # JX1_HP_DP_32_P - FMC_LA09_P set_property PACKAGE_PIN K7 [get_ports {ETH2_RX_D2}]; # JX1_HP_DP_34_N - FMC_LA10_N set_property PACKAGE_PIN U2 [get_ports {ETH2_TX_CLK}]; # JX1_HP_DP_27_N - FMC_LA11_N set_property PACKAGE_PIN T3 [get_ports {ETH2_TX_D1}]; # JX1_HP_DP_27_P - FMC_LA11_P set_property PACKAGE_PIN V3 [get_ports {ETH2_TX_D0}]; # JX1_HP_DP_29_N - FMC_LA12_N set_property PACKAGE_PIN P1 [get_ports {ETH2_MDC}]; # JX1_HP_DP_30_N - FMC_LA13_N set_property PACKAGE_PIN N1 [get_ports {M2C_125MHZ_EN}]; # JX1_HP_DP_30_P - FMC_LA13_P set_property PACKAGE_PIN P2 [get_ports {ETH2_MDIO}]; # JX1_HP_DP_28_N - FMC_LA14_N set_property PACKAGE_PIN P3 [get_ports {M2C_125MHZ_SEL}]; # JX1_HP_DP_28_P - FMC_LA14_P set_property PACKAGE_PIN W7 [get_ports {ETH2_RST_N}]; # JX1_HP_DP_23_N - FMC_LA15_N set_property PACKAGE_PIN W8 [get_ports {ETH2_TX_EN}]; # JX1_HP_DP_23_P - FMC_LA15_P set_property PACKAGE_PIN T7 [get_ports {ETH2_TX_D3}]; # JX1_HP_DP_25_N - FMC_LA16_N set_property PACKAGE_PIN R7 [get_ports {ETH2_TX_D2}]; # JX1_HP_DP_25_P - FMC_LA16_P set_property PACKAGE_PIN AD7 [get_ports {LED4B}]; # JX1_HP_DP_07_N - FMC_LA24_N set_property PACKAGE_PIN AD8 [get_ports {LED4A}]; # JX1_HP_DP_07_P - FMC_LA24_P set_property PACKAGE_PIN Y1 [get_ports {LED3B}]; # JX1_HP_DP_09_N - FMC_LA25_N set_property PACKAGE_PIN W1 [get_ports {LED3A}]; # JX1_HP_DP_09_P - FMC_LA25_P set_property PACKAGE_PIN W2 [get_ports {LED2B}]; # JX1_HP_DP_12_N - FMC_LA26_N set_property PACKAGE_PIN W3 [get_ports {LED2A}]; # JX1_HP_DP_12_P - FMC_LA26_P set_property PACKAGE_PIN AA2 [get_ports {LED1B}]; # JX1_HP_DP_14_N - FMC_LA27_N set_property PACKAGE_PIN Y2 [get_ports {LED1A}]; # JX1_HP_DP_14_P - FMC_LA27_P set_property PACKAGE_PIN AA3 [get_ports {LED5B}]; # JX1_HP_DP_08_N - FMC_LA28_N set_property PACKAGE_PIN AA4 [get_ports {LED5A}]; # JX1_HP_DP_08_P - FMC_LA28_P set_property PACKAGE_PIN B10 [get_ports {FMC_SDA}]; # JX2_HD_SE_01_N - FMC_SDA set_property PACKAGE_PIN C10 [get_ports {FMC_SCL}]; # JX2_HD_SE_01_P - FMC_SCL set_property PACKAGE_PIN AB7 [get_ports {FMC_SCL1}]; # JX1_HP_DP_00_N - FMC_LA32_P set_property PACKAGE_PIN AB8 [get_ports {FMC_SDA1}]; # JX1_HP_DP_00_P - FMC_LA32_N set_property PACKAGE_PIN AE7 [get_ports {FMC_SCL2}]; # JX1_HP_DP_06_P - FMC_LA31_P set_property PACKAGE_PIN AE6 [get_ports {FMC_SDA2}]; # JX1_HP_DP_06_N - FMC_LA31_N set_property PACKAGE_PIN H9 [get_ports {FMC_PRSNT_M2C_N}];# JX2_HD_SE_00_N - FMC_PRSNT_M2C_N set_property PACKAGE_PIN H10 [get_ports {FMC_TRST_N}]; # JX2_HD_SE_00_P - FMC_TRST_N set_property IOSTANDARD LVDS [get_ports {M2C_125MHZ_N}] set_property IOSTANDARD LVDS [get_ports {M2C_125MHZ_P}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH1_RX_EN}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH1_RX_CLK}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH2_RX_EN}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH2_RX_CLK}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH1_RX_D1}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH1_RX_D0}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH1_RX_D3}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH1_RX_D2}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH1_TX_CLK}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH1_TX_D0}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH1_RST_N}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH1_MDC}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH1_MDIO}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH2_RX_D0}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH1_TX_EN}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH1_TX_D3}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH1_TX_D2}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH1_TX_D1}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH2_RX_D3}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH2_RX_D1}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH2_RX_D2}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH2_TX_CLK}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH2_TX_D1}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH2_TX_D0}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH2_MDC}] set_property IOSTANDARD LVCMOS18 [get_ports {M2C_125MHZ_EN}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH2_MDIO}] set_property IOSTANDARD LVCMOS18 [get_ports {M2C_125MHZ_SEL}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH2_RST_N}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH2_TX_EN}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH2_TX_D3}] set_property IOSTANDARD LVCMOS18 [get_ports {ETH2_TX_D2}] set_property IOSTANDARD LVCMOS18 [get_ports {LED4B}] set_property IOSTANDARD LVCMOS18 [get_ports {LED4A}] set_property IOSTANDARD LVCMOS18 [get_ports {LED3B}] set_property IOSTANDARD LVCMOS18 [get_ports {LED3A}] set_property IOSTANDARD LVCMOS18 [get_ports {LED2B}] set_property IOSTANDARD LVCMOS18 [get_ports {LED2A}] set_property IOSTANDARD LVCMOS18 [get_ports {LED1B}] set_property IOSTANDARD LVCMOS18 [get_ports {LED1A}] set_property IOSTANDARD LVCMOS18 [get_ports {LED5B}] set_property IOSTANDARD LVCMOS18 [get_ports {LED5A}] set_property IOSTANDARD LVCMOS18 [get_ports {FMC_SDA1}] set_property IOSTANDARD LVCMOS18 [get_ports {FMC_SCL1}] set_property IOSTANDARD LVCMOS18 [get_ports {FMC_SDA2}] set_property IOSTANDARD LVCMOS18 [get_ports {FMC_SCL2}] set_property IOSTANDARD LVCMOS33 [get_ports {FMC_SDA}] set_property IOSTANDARD LVCMOS33 [get_ports {FMC_SCL}] set_property IOSTANDARD LVCMOS33 [get_ports {FMC_PRSNT_M2C_N}] set_property IOSTANDARD LVCMOS33 [get_ports {FMC_TRST_N}] set_property PACKAGE_PIN AB7 [get_ports {FMC_SCL1}]; # JX1_HP_DP_00_N set_property PACKAGE_PIN AB8 [get_ports {FMC_SDA1}]; # JX1_HP_DP_00_P set_property PACKAGE_PIN AE7 [get_ports {FMC_SCL2}]; # JX1_HP_DP_06_P set_property PACKAGE_PIN AE6 [get_ports {FMC_SDA2}]; # JX1_HP_DP_06_N