#-----------------------------------------------------------
# Vivado v2015.1 (64-bit)
# SW Build 1215546 on Mon Apr 27 19:22:08 MDT 2015
# IP Build 1209967 on Tue Apr 21 11:39:20 MDT 2015
# Start of session at: Fri Jul 31 07:42:12 2015
# Process ID: 6576
# Log file: C:/XLX/MZCC_ARD_7020/MZCC_ARD_7020.runs/impl_2/tutorial_wrapper.vdi
# Journal file: C:/XLX/MZCC_ARD_7020/MZCC_ARD_7020.runs/impl_2\vivado.jou
#-----------------------------------------------------------
source tutorial_wrapper.tcl -notrace
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 6 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2015.1
INFO: [Device 21-403] Loading part xc7z020clg400-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [c:/XLX/MZCC_ARD_7020/MZCC_ARD_7020.srcs/sources_1/bd/tutorial/ip/tutorial_processing_system7_0_0/tutorial_processing_system7_0_0.xdc] for cell 'tutorial_i/processing_system7_0/inst'
Finished Parsing XDC File [c:/XLX/MZCC_ARD_7020/MZCC_ARD_7020.srcs/sources_1/bd/tutorial/ip/tutorial_processing_system7_0_0/tutorial_processing_system7_0_0.xdc] for cell 'tutorial_i/processing_system7_0/inst'
Parsing XDC File [C:/XLX/MZCC_ARD_7020/MZCC_ARD_7020.srcs/ARDCC.xps/imports/constraints/MZCC_ARD_constraints.xdc]
Finished Parsing XDC File [C:/XLX/MZCC_ARD_7020/MZCC_ARD_7020.srcs/ARDCC.xps/imports/constraints/MZCC_ARD_constraints.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
  A total of 2 instances were transformed.
  IOBUF => IOBUF (IBUF, OBUFT): 2 instances

link_design: Time (s): cpu = 00:00:05 ; elapsed = 00:00:06 . Memory (MB): peak = 470.555 ; gain = 274.617
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-1223] The version limit for your license is '2015.06' and will expire in -31 days. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.072 . Memory (MB): peak = 475.020 ; gain = 1.270
INFO: [Timing 38-35] Done setting XDC timing constraints.

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 1d13d9ff7

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.133 . Memory (MB): peak = 873.824 ; gain = 0.020

Phase 2 Constant Propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-10] Eliminated 0 cells.
Phase 2 Constant Propagation | Checksum: 1d13d9ff7

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.172 . Memory (MB): peak = 873.824 ; gain = 0.020

Phase 3 Sweep
INFO: [Opt 31-12] Eliminated 18 unconnected nets.
INFO: [Opt 31-11] Eliminated 28 unconnected cells.
Phase 3 Sweep | Checksum: 14ee9807a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.329 . Memory (MB): peak = 873.824 ; gain = 0.020

Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 873.824 ; gain = 0.000
Ending Logic Optimization Task | Checksum: 14ee9807a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.330 . Memory (MB): peak = 873.824 ; gain = 0.020
Implement Debug Cores | Checksum: 1f25b9645
Logic Optimization | Checksum: 1f25b9645

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 3.13 ns.
Ending Power Optimization Task | Checksum: 14ee9807a

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.006 . Memory (MB): peak = 873.824 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 873.824 ; gain = 403.270
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.093 . Memory (MB): peak = 873.824 ; gain = 0.000
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/XLX/MZCC_ARD_7020/MZCC_ARD_7020.runs/impl_2/tutorial_wrapper_drc_opted.rpt.
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-1223] The version limit for your license is '2015.06' and will expire in -31 days. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Runtime Estimator
Phase 1 Placer Runtime Estimator | Checksum: dc5154eb

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 890.629 ; gain = 0.000

Phase 2 Placer Initialization
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 890.629 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 890.629 ; gain = 0.000

Phase 2.1 IO Placement/ Clock Placement/ Build Placer Device

Phase 2.1.1 Pre-Place Cells
Phase 2.1.1 Pre-Place Cells | Checksum: db732882

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.043 . Memory (MB): peak = 890.629 ; gain = 0.000
WARNING: [Place 30-12] An IO Bus FIXED_IO_mio with more than one IO standard is found. Components associated with this bus are: 
	FIXED_IO_mio[53] of IOStandard LVCMOS18
	FIXED_IO_mio[52] of IOStandard LVCMOS18
	FIXED_IO_mio[51] of IOStandard LVCMOS18
	FIXED_IO_mio[50] of IOStandard LVCMOS18
	FIXED_IO_mio[49] of IOStandard LVCMOS18
	FIXED_IO_mio[48] of IOStandard LVCMOS18
	FIXED_IO_mio[47] of IOStandard LVCMOS18
	FIXED_IO_mio[46] of IOStandard LVCMOS18
	FIXED_IO_mio[45] of IOStandard LVCMOS18
	FIXED_IO_mio[44] of IOStandard LVCMOS18
	FIXED_IO_mio[43] of IOStandard LVCMOS18
	FIXED_IO_mio[42] of IOStandard LVCMOS18
	FIXED_IO_mio[41] of IOStandard LVCMOS18
	FIXED_IO_mio[40] of IOStandard LVCMOS18
	FIXED_IO_mio[39] of IOStandard LVCMOS18
	FIXED_IO_mio[38] of IOStandard LVCMOS18
	FIXED_IO_mio[37] of IOStandard LVCMOS18
	FIXED_IO_mio[36] of IOStandard LVCMOS18
	FIXED_IO_mio[35] of IOStandard LVCMOS18
	FIXED_IO_mio[34] of IOStandard LVCMOS18
	FIXED_IO_mio[33] of IOStandard LVCMOS18
	FIXED_IO_mio[32] of IOStandard LVCMOS18
	FIXED_IO_mio[31] of IOStandard LVCMOS18
	FIXED_IO_mio[30] of IOStandard LVCMOS18
	FIXED_IO_mio[29] of IOStandard LVCMOS18
	FIXED_IO_mio[28] of IOStandard LVCMOS18
	FIXED_IO_mio[27] of IOStandard LVCMOS18
	FIXED_IO_mio[26] of IOStandard LVCMOS18
	FIXED_IO_mio[25] of IOStandard LVCMOS18
	FIXED_IO_mio[24] of IOStandard LVCMOS18
	FIXED_IO_mio[23] of IOStandard LVCMOS18
	FIXED_IO_mio[22] of IOStandard LVCMOS18
	FIXED_IO_mio[21] of IOStandard LVCMOS18
	FIXED_IO_mio[20] of IOStandard LVCMOS18
	FIXED_IO_mio[19] of IOStandard LVCMOS18
	FIXED_IO_mio[18] of IOStandard LVCMOS18
	FIXED_IO_mio[17] of IOStandard LVCMOS18
	FIXED_IO_mio[16] of IOStandard LVCMOS18
	FIXED_IO_mio[15] of IOStandard LVCMOS33
	FIXED_IO_mio[14] of IOStandard LVCMOS33
	FIXED_IO_mio[13] of IOStandard LVCMOS33
	FIXED_IO_mio[12] of IOStandard LVCMOS33
	FIXED_IO_mio[11] of IOStandard LVCMOS33
	FIXED_IO_mio[10] of IOStandard LVCMOS33
	FIXED_IO_mio[9] of IOStandard LVCMOS33
	FIXED_IO_mio[8] of IOStandard LVCMOS33
	FIXED_IO_mio[7] of IOStandard LVCMOS33
	FIXED_IO_mio[6] of IOStandard LVCMOS33
	FIXED_IO_mio[5] of IOStandard LVCMOS33
	FIXED_IO_mio[4] of IOStandard LVCMOS33
	FIXED_IO_mio[3] of IOStandard LVCMOS33
	FIXED_IO_mio[2] of IOStandard LVCMOS33
	FIXED_IO_mio[1] of IOStandard LVCMOS33
	FIXED_IO_mio[0] of IOStandard LVCMOS33
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 2.1.2 IO & Clk Clean Up
Phase 2.1.2 IO & Clk Clean Up | Checksum: db732882

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.875 . Memory (MB): peak = 896.055 ; gain = 5.426

Phase 2.1.3 Implementation Feasibility check On IDelay
Phase 2.1.3 Implementation Feasibility check On IDelay | Checksum: db732882

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.876 . Memory (MB): peak = 896.055 ; gain = 5.426

Phase 2.1.4 Commit IO Placement
Phase 2.1.4 Commit IO Placement | Checksum: db732882

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.877 . Memory (MB): peak = 896.055 ; gain = 5.426
Phase 2.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 11ecbe768

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.878 . Memory (MB): peak = 896.055 ; gain = 5.426

Phase 2.2 Build Placer Netlist Model

Phase 2.2.1 Place Init Design
Phase 2.2.1 Place Init Design | Checksum: 1d6369979

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.886 . Memory (MB): peak = 896.055 ; gain = 5.426
Phase 2.2 Build Placer Netlist Model | Checksum: 1d6369979

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.886 . Memory (MB): peak = 896.055 ; gain = 5.426

Phase 2.3 Constrain Clocks/Macros

Phase 2.3.1 Constrain Global/Regional Clocks
Phase 2.3.1 Constrain Global/Regional Clocks | Checksum: 1d6369979

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.889 . Memory (MB): peak = 896.055 ; gain = 5.426
Phase 2.3 Constrain Clocks/Macros | Checksum: 1d6369979

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.889 . Memory (MB): peak = 896.055 ; gain = 5.426
Phase 2 Placer Initialization | Checksum: 1d6369979

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.890 . Memory (MB): peak = 896.055 ; gain = 5.426

Phase 3 Global Placement
Phase 3 Global Placement | Checksum: 173e59a40

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 896.055 ; gain = 5.426

Phase 4 Detail Placement

Phase 4.1 Commit Multi Column Macros
Phase 4.1 Commit Multi Column Macros | Checksum: 173e59a40

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 896.055 ; gain = 5.426

Phase 4.2 Commit Most Macros & LUTRAMs
Phase 4.2 Commit Most Macros & LUTRAMs | Checksum: 152db0104

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 896.055 ; gain = 5.426

Phase 4.3 Area Swap Optimization
Phase 4.3 Area Swap Optimization | Checksum: 1d586283c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 896.055 ; gain = 5.426

Phase 4.4 Small Shape Detail Placement

Phase 4.4.1 Commit Small Macros & Core Logic

Phase 4.4.1.1 Commit Slice Clusters
Phase 4.4.1.1 Commit Slice Clusters | Checksum: 1d63746cc

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 896.055 ; gain = 5.426
Phase 4.4.1 Commit Small Macros & Core Logic | Checksum: 1d63746cc

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 896.055 ; gain = 5.426

Phase 4.4.2 Clock Restriction Legalization for Leaf Columns
Phase 4.4.2 Clock Restriction Legalization for Leaf Columns | Checksum: 1d63746cc

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 896.055 ; gain = 5.426

Phase 4.4.3 Clock Restriction Legalization for Non-Clock Pins
Phase 4.4.3 Clock Restriction Legalization for Non-Clock Pins | Checksum: 1d63746cc

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 896.055 ; gain = 5.426
Phase 4.4 Small Shape Detail Placement | Checksum: 1d63746cc

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 896.055 ; gain = 5.426

Phase 4.5 Re-assign LUT pins
Phase 4.5 Re-assign LUT pins | Checksum: 1d63746cc

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 896.055 ; gain = 5.426
Phase 4 Detail Placement | Checksum: 1d63746cc

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 896.055 ; gain = 5.426

Phase 5 Post Placement Optimization and Clean-Up

Phase 5.1 PCOPT Shape updates
Phase 5.1 PCOPT Shape updates | Checksum: 1d63746cc

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 896.055 ; gain = 5.426

Phase 5.2 Post Commit Optimization
Phase 5.2 Post Commit Optimization | Checksum: 1d63746cc

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 896.055 ; gain = 5.426

Phase 5.3 Sweep Clock Roots: Post-Placement
Phase 5.3 Sweep Clock Roots: Post-Placement | Checksum: 1d63746cc

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 896.055 ; gain = 5.426

Phase 5.4 Post Placement Cleanup
Phase 5.4 Post Placement Cleanup | Checksum: 1d63746cc

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 896.055 ; gain = 5.426

Phase 5.5 Placer Reporting
Phase 5.5 Placer Reporting | Checksum: 1d63746cc

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 896.055 ; gain = 5.426

Phase 5.6 Final Placement Cleanup
Phase 5.6 Final Placement Cleanup | Checksum: 1d63746cc

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 896.055 ; gain = 5.426
Phase 5 Post Placement Optimization and Clean-Up | Checksum: 1d63746cc

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 896.055 ; gain = 5.426
Ending Placer Task | Checksum: 100cc9cec

Time (s): cpu = 00:00:02 ; elapsed = 00:00:01 . Memory (MB): peak = 896.055 ; gain = 5.426
INFO: [Common 17-83] Releasing license: Implementation
34 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.110 . Memory (MB): peak = 896.055 ; gain = 0.000
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.057 . Memory (MB): peak = 896.055 ; gain = 0.000
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.051 . Memory (MB): peak = 896.055 ; gain = 0.000
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.003 . Memory (MB): peak = 896.055 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-1223] The version limit for your license is '2015.06' and will expire in -31 days. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
WARNING: [DRC 23-20] Rule violation (PLIO-7) Placement Constraints Check for IO constraints - An IO Bus FIXED_IO_mio[53:0] with more than one IO standard is found. Components associated with this bus are:  FIXED_IO_mio[53] of IOStandard LVCMOS18; FIXED_IO_mio[52] of IOStandard LVCMOS18; FIXED_IO_mio[51] of IOStandard LVCMOS18; FIXED_IO_mio[50] of IOStandard LVCMOS18; FIXED_IO_mio[49] of IOStandard LVCMOS18; FIXED_IO_mio[48] of IOStandard LVCMOS18; FIXED_IO_mio[47] of IOStandard LVCMOS18; FIXED_IO_mio[46] of IOStandard LVCMOS18; FIXED_IO_mio[45] of IOStandard LVCMOS18; FIXED_IO_mio[44] of IOStandard LVCMOS18; FIXED_IO_mio[43] of IOStandard LVCMOS18; FIXED_IO_mio[42] of IOStandard LVCMOS18; FIXED_IO_mio[41] of IOStandard LVCMOS18; FIXED_IO_mio[40] of IOStandard LVCMOS18; FIXED_IO_mio[39] of IOStandard LVCMOS18; FIXED_IO_mio[38] of IOStandard LVCMOS18; FIXED_IO_mio[37] of IOStandard LVCMOS18; FIXED_IO_mio[36] of IOStandard LVCMOS18; FIXED_IO_mio[35] of IOStandard LVCMOS18; FIXED_IO_mio[34] of IOStandard LVCMOS18; FIXED_IO_mio[33] of IOStandard LVCMOS18; FIXED_IO_mio[32] of IOStandard LVCMOS18; FIXED_IO_mio[31] of IOStandard LVCMOS18; FIXED_IO_mio[30] of IOStandard LVCMOS18; FIXED_IO_mio[29] of IOStandard LVCMOS18; FIXED_IO_mio[28] of IOStandard LVCMOS18; FIXED_IO_mio[27] of IOStandard LVCMOS18; FIXED_IO_mio[26] of IOStandard LVCMOS18; FIXED_IO_mio[25] of IOStandard LVCMOS18; FIXED_IO_mio[24] of IOStandard LVCMOS18; FIXED_IO_mio[23] of IOStandard LVCMOS18; FIXED_IO_mio[22] of IOStandard LVCMOS18; FIXED_IO_mio[21] of IOStandard LVCMOS18; FIXED_IO_mio[20] of IOStandard LVCMOS18; FIXED_IO_mio[19] of IOStandard LVCMOS18; FIXED_IO_mio[18] of IOStandard LVCMOS18; FIXED_IO_mio[17] of IOStandard LVCMOS18; FIXED_IO_mio[16] of IOStandard LVCMOS18; FIXED_IO_mio[15] of IOStandard LVCMOS33; FIXED_IO_mio[14] of IOStandard LVCMOS33; FIXED_IO_mio[13] of IOStandard LVCMOS33; FIXED_IO_mio[12] of IOStandard LVCMOS33; FIXED_IO_mio[11] of IOStandard LVCMOS33; FIXED_IO_mio[10] of IOStandard LVCMOS33; FIXED_IO_mio[9] of IOStandard LVCMOS33; FIXED_IO_mio[8] of IOStandard LVCMOS33; FIXED_IO_mio[7] of IOStandard LVCMOS33; FIXED_IO_mio[6] of IOStandard LVCMOS33; FIXED_IO_mio[5] of IOStandard LVCMOS33; FIXED_IO_mio[4] of IOStandard LVCMOS33; FIXED_IO_mio[3] of IOStandard LVCMOS33; FIXED_IO_mio[2] of IOStandard LVCMOS33; FIXED_IO_mio[1] of IOStandard LVCMOS33; FIXED_IO_mio[0] of IOStandard LVCMOS33;
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: d25f6f39

Time (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 1038.254 ; gain = 135.836

Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.

Phase 2.1 Pre Route Cleanup
Phase 2.1 Pre Route Cleanup | Checksum: d25f6f39

Time (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 1043.281 ; gain = 140.863
 Number of Nodes with overlaps = 0
Phase 2 Router Initialization | Checksum: 16427f387

Time (s): cpu = 00:00:31 ; elapsed = 00:00:28 . Memory (MB): peak = 1045.875 ; gain = 143.457

Phase 3 Initial Routing
 Number of Nodes with overlaps = 0
Phase 3 Initial Routing | Checksum: 17048ccef

Time (s): cpu = 00:00:32 ; elapsed = 00:00:28 . Memory (MB): peak = 1045.875 ; gain = 143.457

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
Phase 4.1 Global Iteration 0 | Checksum: 17048ccef

Time (s): cpu = 00:00:32 ; elapsed = 00:00:28 . Memory (MB): peak = 1045.875 ; gain = 143.457

Phase 4.2 Global Iteration 1
Phase 4.2 Global Iteration 1 | Checksum: 17048ccef

Time (s): cpu = 00:00:32 ; elapsed = 00:00:28 . Memory (MB): peak = 1045.875 ; gain = 143.457

Phase 4.3 Global Iteration 2
Phase 4.3 Global Iteration 2 | Checksum: 17048ccef

Time (s): cpu = 00:00:32 ; elapsed = 00:00:28 . Memory (MB): peak = 1045.875 ; gain = 143.457

Phase 4.4 Global Iteration 3
Phase 4.4 Global Iteration 3 | Checksum: 17048ccef

Time (s): cpu = 00:00:32 ; elapsed = 00:00:28 . Memory (MB): peak = 1045.875 ; gain = 143.457

Phase 4.5 Global Iteration 4
Phase 4.5 Global Iteration 4 | Checksum: 17048ccef

Time (s): cpu = 00:00:32 ; elapsed = 00:00:28 . Memory (MB): peak = 1045.875 ; gain = 143.457
Phase 4 Rip-up And Reroute | Checksum: 17048ccef

Time (s): cpu = 00:00:32 ; elapsed = 00:00:28 . Memory (MB): peak = 1045.875 ; gain = 143.457

Phase 5 Delay and Skew Optimization
Phase 5 Delay and Skew Optimization | Checksum: 17048ccef

Time (s): cpu = 00:00:32 ; elapsed = 00:00:28 . Memory (MB): peak = 1045.875 ; gain = 143.457

Phase 6 Post Hold Fix
Phase 6 Post Hold Fix | Checksum: 17048ccef

Time (s): cpu = 00:00:32 ; elapsed = 00:00:28 . Memory (MB): peak = 1045.875 ; gain = 143.457

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.0442166 %
  Global Horizontal Routing Utilization  = 0.0922076 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Congestion Report
North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 32.3529%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 17.6471%, No Congested Regions.
Phase 7 Route finalize | Checksum: 17048ccef

Time (s): cpu = 00:00:32 ; elapsed = 00:00:28 . Memory (MB): peak = 1045.875 ; gain = 143.457

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: 17048ccef

Time (s): cpu = 00:00:32 ; elapsed = 00:00:28 . Memory (MB): peak = 1046.746 ; gain = 144.328

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: 114caa26c

Time (s): cpu = 00:00:32 ; elapsed = 00:00:28 . Memory (MB): peak = 1046.746 ; gain = 144.328
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:00:32 ; elapsed = 00:00:28 . Memory (MB): peak = 1046.746 ; gain = 144.328

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
43 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:33 ; elapsed = 00:00:29 . Memory (MB): peak = 1046.746 ; gain = 150.691
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.086 . Memory (MB): peak = 1046.746 ; gain = 0.000
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/XLX/MZCC_ARD_7020/MZCC_ARD_7020.runs/impl_2/tutorial_wrapper_drc_routed.rpt.
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
WARNING: [Power 33-232] No user defined clocks were found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
INFO: [Common 17-206] Exiting Vivado at Fri Jul 31 07:43:07 2015...
