Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
| Date         : Wed Jul 29 12:21:36 2015
| Host         : Peter_S55T running 64-bit major release  (build 9200)
| Command      : upgrade_ip
| Device       : xc7z020clg400-1
------------------------------------------------------------------------------------

Upgrade Log for IP 'tutorial_processing_system7_0_0'

1. Summary
----------

SUCCESS in the update of tutorial_processing_system7_0_0 (xilinx.com:ip:processing_system7:5.5 (Rev. 1)) to current project options.

2. Upgrade messages
-------------------

WARNING: upgrade cannot add parameter PCW_TRACE_INTERNAL_WIDTH with default value 32 : a parameter called PCW_TRACE_INTERNAL_WIDTH already exists in processing_system7_v5_5
WARNING: upgrade cannot add parameter PCW_USE_AXI_NONSECURE with default value 0 : a parameter called PCW_USE_AXI_NONSECURE already exists in processing_system7_v5_5






Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
| Date         : Tue Jul 28 18:14:36 2015
| Host         : Peter_S55T running 64-bit major release  (build 9200)
| Command      : upgrade_ip
| Device       : xc7z020clg484-1
------------------------------------------------------------------------------------

Upgrade Log for IP 'tutorial_processing_system7_0_0'

1. Summary
----------

SUCCESS in the update of tutorial_processing_system7_0_0 (xilinx.com:ip:processing_system7:5.5 (Rev. 1)) to current project options.

2. Upgrade messages
-------------------

WARNING: upgrade cannot add parameter PCW_TRACE_INTERNAL_WIDTH with default value 32 : a parameter called PCW_TRACE_INTERNAL_WIDTH already exists in processing_system7_v5_5
WARNING: upgrade cannot add parameter PCW_USE_AXI_NONSECURE with default value 0 : a parameter called PCW_USE_AXI_NONSECURE already exists in processing_system7_v5_5






Copyright 1986-2015 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2015.1 (win64) Build 1215546 Mon Apr 27 19:22:08 MDT 2015
| Date         : Tue Jun 30 13:58:38 2015
| Host         : Peter_S55T running 64-bit major release  (build 9200)
| Command      : upgrade_ip
| Device       : xc7z020clg400-1
------------------------------------------------------------------------------------

Upgrade Log for IP 'tutorial_processing_system7_0_0'

1. Summary
----------

CAUTION (success, with warnings) in the upgrade of tutorial_processing_system7_0_0 from xilinx.com:ip:processing_system7:5.4 (Rev. 1) to xilinx.com:ip:processing_system7:5.5 (Rev. 1)

After upgrade, an IP may have parameter and port differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality. Also, please review the updated IP instantiation template to ensure proper connectivity, and update your design if required.

2. Warnings
-----------

WARNING: 1. The custom time stamp unit(PTP) signals will be exposed to the Programmable Logic(PL),  
  even when the Ethernet is routed through the MIO. For more details 
,  please refer Zynq Technical Reference Manual (UG 585) CH No. 16.4 IEEE 1588 Time Stamping. 
 This change enables additional optional functionality for designs with Ethernet on MIO. 
 No changes are required for existing designs. 
  2. Updated the JTAG interface from master to slave mode. Based on Zynq Technical Reference Manual, 
  PS boot mode supports 4 master boot mode and 2 Slave JTAG Boot mode. Prior versions of Zynq PS7 
  IP had PL JTAG in master mode incorrectly. The JTAG port TDO will have a buffer (OBUFT) 
  instantiated as part of the Processing System7 IP. This change only affects designs which use PL JTAG 
  through EMIO interface. For More details, refer chapter no.6 of Zynq Technical Reference Manual 
  (UG 585) - Boot and Configuration. 


3. Interface Information
------------------------

Detected external interface differences while upgrading IP 'tutorial_processing_system7_0_0'.


-upgraded interface 'PJTAG' (xilinx.com:interface:jtag:2.0) differs from original interface xilinx.com:interface:jtag:1.0

4. Connection Warnings
----------------------

Detected external port differences while upgrading IP 'tutorial_processing_system7_0_0'. These changes may impact your design.


-upgrade has added port 'ENET0_PTP_DELAY_REQ_RX'
-upgrade has added port 'ENET0_PTP_DELAY_REQ_TX'
-upgrade has added port 'ENET0_PTP_PDELAY_REQ_RX'
-upgrade has added port 'ENET0_PTP_PDELAY_REQ_TX'
-upgrade has added port 'ENET0_PTP_PDELAY_RESP_RX'
-upgrade has added port 'ENET0_PTP_PDELAY_RESP_TX'
-upgrade has added port 'ENET0_PTP_SYNC_FRAME_RX'
-upgrade has added port 'ENET0_PTP_SYNC_FRAME_TX'
-upgrade has added port 'ENET0_SOF_RX'
-upgrade has added port 'ENET0_SOF_TX'

5. Upgrade messages
-------------------

Added parameter PCW_TRACE_INTERNAL_WIDTH with value 32
Added parameter PCW_USE_AXI_NONSECURE with value 0

