#-----------------------------------------------------------
# Vivado v2015.1 (64-bit)
# SW Build 1215546 on Mon Apr 27 19:22:08 MDT 2015
# IP Build 1209967 on Tue Apr 21 11:39:20 MDT 2015
# Start of session at: Wed Jul 29 16:33:28 2015
# Process ID: 9688
# Log file: C:/XLX/MZCC_ARD_7020/MZCC_ARD_7020.runs/impl_2/tutorial_wrapper.vdi
# Journal file: C:/XLX/MZCC_ARD_7020/MZCC_ARD_7020.runs/impl_2\vivado.jou
#-----------------------------------------------------------
source tutorial_wrapper.tcl -notrace
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
INFO: [Netlist 29-17] Analyzing 3 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2015.1
INFO: [Device 21-403] Loading part xc7z020clg400-1
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [c:/XLX/MZCC_ARD_7020/MZCC_ARD_7020.srcs/sources_1/bd/tutorial/ip/tutorial_processing_system7_0_0/tutorial_processing_system7_0_0.xdc] for cell 'tutorial_i/processing_system7_0/inst'
Finished Parsing XDC File [c:/XLX/MZCC_ARD_7020/MZCC_ARD_7020.srcs/sources_1/bd/tutorial/ip/tutorial_processing_system7_0_0/tutorial_processing_system7_0_0.xdc] for cell 'tutorial_i/processing_system7_0/inst'
Parsing XDC File [C:/XLX/MZCC_ARD_7020/MZCC_ARD_7020.srcs/constrs_1/imports/constraints/MZCC_ARD_constraints.xdc]
Finished Parsing XDC File [C:/XLX/MZCC_ARD_7020/MZCC_ARD_7020.srcs/constrs_1/imports/constraints/MZCC_ARD_constraints.xdc]
Parsing XDC File [C:/XLX/MZCC_ARD_7020/MZCC_ARD_7020.srcs/constrs_1/new/New constraints.xdc]
Finished Parsing XDC File [C:/XLX/MZCC_ARD_7020/MZCC_ARD_7020.srcs/constrs_1/new/New constraints.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.

link_design: Time (s): cpu = 00:00:06 ; elapsed = 00:00:06 . Memory (MB): peak = 470.625 ; gain = 274.598
Command: opt_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-1223] The version limit for your license is '2015.06' and will expire in -29 days. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
Running DRC as a precondition to command opt_design

Starting DRC Task
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Project 1-461] DRC finished with 0 Errors
INFO: [Project 1-462] Please refer to the DRC report (report_drc) for more information.

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.070 . Memory (MB): peak = 475.141 ; gain = 1.195
INFO: [Timing 38-35] Done setting XDC timing constraints.

Starting Logic Optimization Task

Phase 1 Retarget
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-49] Retargeted 0 cell(s).
Phase 1 Retarget | Checksum: 233fe7fce

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.141 . Memory (MB): peak = 873.793 ; gain = 0.020

Phase 2 Constant Propagation
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Opt 31-10] Eliminated 0 cells.
Phase 2 Constant Propagation | Checksum: 233fe7fce

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.181 . Memory (MB): peak = 873.793 ; gain = 0.020

Phase 3 Sweep
INFO: [Opt 31-12] Eliminated 16 unconnected nets.
INFO: [Opt 31-11] Eliminated 29 unconnected cells.
Phase 3 Sweep | Checksum: e4c37031

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.345 . Memory (MB): peak = 873.793 ; gain = 0.020

Starting Connectivity Check Task

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 873.793 ; gain = 0.000
Ending Logic Optimization Task | Checksum: e4c37031

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.346 . Memory (MB): peak = 873.793 ; gain = 0.020
Implement Debug Cores | Checksum: 238c31802
Logic Optimization | Checksum: 238c31802

Starting Power Optimization Task
INFO: [Pwropt 34-132] Skipping clock gating for clocks with a period < 3.13 ns.
Ending Power Optimization Task | Checksum: e4c37031

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.007 . Memory (MB): peak = 873.793 ; gain = 0.000
INFO: [Common 17-83] Releasing license: Implementation
21 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
opt_design completed successfully
opt_design: Time (s): cpu = 00:00:12 ; elapsed = 00:00:12 . Memory (MB): peak = 873.793 ; gain = 403.168
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.072 . Memory (MB): peak = 873.793 ; gain = 0.000
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/XLX/MZCC_ARD_7020/MZCC_ARD_7020.runs/impl_2/tutorial_wrapper_drc_opted.rpt.
Command: place_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-1223] The version limit for your license is '2015.06' and will expire in -29 days. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.
Running DRC as a precondition to command place_design
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.

Starting Placer Task
INFO: [Place 30-611] Multithreading enabled for place_design using a maximum of 2 CPUs

Phase 1 Placer Runtime Estimator
Phase 1 Placer Runtime Estimator | Checksum: dd3b3157

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.018 . Memory (MB): peak = 892.477 ; gain = 0.000

Phase 2 Placer Initialization
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.002 . Memory (MB): peak = 892.477 ; gain = 0.000
Netlist sorting complete. Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.001 . Memory (MB): peak = 892.477 ; gain = 0.000

Phase 2.1 IO Placement/ Clock Placement/ Build Placer Device

Phase 2.1.1 Pre-Place Cells
Phase 2.1.1 Pre-Place Cells | Checksum: 8694bc0c

Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.047 . Memory (MB): peak = 892.477 ; gain = 0.000
WARNING: [Place 30-12] An IO Bus FIXED_IO_mio with more than one IO standard is found. Components associated with this bus are: 
	FIXED_IO_mio[53] of IOStandard LVCMOS18
	FIXED_IO_mio[52] of IOStandard LVCMOS18
	FIXED_IO_mio[51] of IOStandard LVCMOS18
	FIXED_IO_mio[50] of IOStandard LVCMOS18
	FIXED_IO_mio[49] of IOStandard LVCMOS18
	FIXED_IO_mio[48] of IOStandard LVCMOS18
	FIXED_IO_mio[47] of IOStandard LVCMOS18
	FIXED_IO_mio[46] of IOStandard LVCMOS18
	FIXED_IO_mio[45] of IOStandard LVCMOS18
	FIXED_IO_mio[44] of IOStandard LVCMOS18
	FIXED_IO_mio[43] of IOStandard LVCMOS18
	FIXED_IO_mio[42] of IOStandard LVCMOS18
	FIXED_IO_mio[41] of IOStandard LVCMOS18
	FIXED_IO_mio[40] of IOStandard LVCMOS18
	FIXED_IO_mio[39] of IOStandard LVCMOS18
	FIXED_IO_mio[38] of IOStandard LVCMOS18
	FIXED_IO_mio[37] of IOStandard LVCMOS18
	FIXED_IO_mio[36] of IOStandard LVCMOS18
	FIXED_IO_mio[35] of IOStandard LVCMOS18
	FIXED_IO_mio[34] of IOStandard LVCMOS18
	FIXED_IO_mio[33] of IOStandard LVCMOS18
	FIXED_IO_mio[32] of IOStandard LVCMOS18
	FIXED_IO_mio[31] of IOStandard LVCMOS18
	FIXED_IO_mio[30] of IOStandard LVCMOS18
	FIXED_IO_mio[29] of IOStandard LVCMOS18
	FIXED_IO_mio[28] of IOStandard LVCMOS18
	FIXED_IO_mio[27] of IOStandard LVCMOS18
	FIXED_IO_mio[26] of IOStandard LVCMOS18
	FIXED_IO_mio[25] of IOStandard LVCMOS18
	FIXED_IO_mio[24] of IOStandard LVCMOS18
	FIXED_IO_mio[23] of IOStandard LVCMOS18
	FIXED_IO_mio[22] of IOStandard LVCMOS18
	FIXED_IO_mio[21] of IOStandard LVCMOS18
	FIXED_IO_mio[20] of IOStandard LVCMOS18
	FIXED_IO_mio[19] of IOStandard LVCMOS18
	FIXED_IO_mio[18] of IOStandard LVCMOS18
	FIXED_IO_mio[17] of IOStandard LVCMOS18
	FIXED_IO_mio[16] of IOStandard LVCMOS18
	FIXED_IO_mio[15] of IOStandard LVCMOS33
	FIXED_IO_mio[14] of IOStandard LVCMOS33
	FIXED_IO_mio[13] of IOStandard LVCMOS33
	FIXED_IO_mio[12] of IOStandard LVCMOS33
	FIXED_IO_mio[11] of IOStandard LVCMOS33
	FIXED_IO_mio[10] of IOStandard LVCMOS33
	FIXED_IO_mio[9] of IOStandard LVCMOS33
	FIXED_IO_mio[8] of IOStandard LVCMOS33
	FIXED_IO_mio[7] of IOStandard LVCMOS33
	FIXED_IO_mio[6] of IOStandard LVCMOS33
	FIXED_IO_mio[5] of IOStandard LVCMOS33
	FIXED_IO_mio[4] of IOStandard LVCMOS33
	FIXED_IO_mio[3] of IOStandard LVCMOS33
	FIXED_IO_mio[2] of IOStandard LVCMOS33
	FIXED_IO_mio[1] of IOStandard LVCMOS33
	FIXED_IO_mio[0] of IOStandard LVCMOS33
INFO: [Timing 38-35] Done setting XDC timing constraints.

Phase 2.1.2 IO & Clk Clean Up
Phase 2.1.2 IO & Clk Clean Up | Checksum: 8694bc0c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.957 . Memory (MB): peak = 897.359 ; gain = 4.883

Phase 2.1.3 Implementation Feasibility check On IDelay
Phase 2.1.3 Implementation Feasibility check On IDelay | Checksum: 8694bc0c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.959 . Memory (MB): peak = 897.359 ; gain = 4.883

Phase 2.1.4 Commit IO Placement
Phase 2.1.4 Commit IO Placement | Checksum: 8694bc0c

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.959 . Memory (MB): peak = 897.359 ; gain = 4.883
Phase 2.1 IO Placement/ Clock Placement/ Build Placer Device | Checksum: 1440d0f21

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.961 . Memory (MB): peak = 897.359 ; gain = 4.883

Phase 2.2 Build Placer Netlist Model

Phase 2.2.1 Place Init Design
Phase 2.2.1 Place Init Design | Checksum: 147598a11

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.968 . Memory (MB): peak = 897.359 ; gain = 4.883
Phase 2.2 Build Placer Netlist Model | Checksum: 147598a11

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.969 . Memory (MB): peak = 897.359 ; gain = 4.883

Phase 2.3 Constrain Clocks/Macros
Phase 2.3 Constrain Clocks/Macros | Checksum: 147598a11

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.969 . Memory (MB): peak = 897.359 ; gain = 4.883
Phase 2 Placer Initialization | Checksum: 147598a11

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.970 . Memory (MB): peak = 897.359 ; gain = 4.883

Phase 3 Final Placement Cleanup
Phase 3 Final Placement Cleanup | Checksum: 147598a11

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.971 . Memory (MB): peak = 897.359 ; gain = 4.883
INFO: [Place 30-281] No place-able instance is found; design doesn't contain any instance or all instances are placed
Ending Placer Task | Checksum: 1440d0f21

Time (s): cpu = 00:00:01 ; elapsed = 00:00:00.974 . Memory (MB): peak = 897.359 ; gain = 4.883
INFO: [Common 17-83] Releasing license: Implementation
35 Infos, 1 Warnings, 0 Critical Warnings and 0 Errors encountered.
place_design completed successfully
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.074 . Memory (MB): peak = 897.359 ; gain = 0.000
report_io: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.053 . Memory (MB): peak = 897.359 ; gain = 0.000
report_utilization: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.052 . Memory (MB): peak = 897.359 ; gain = 0.000
report_control_sets: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.004 . Memory (MB): peak = 897.359 ; gain = 0.000
Command: route_design
Attempting to get a license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7z020'
INFO: [Common 17-1223] The version limit for your license is '2015.06' and will expire in -29 days. A version limit expiration means that, although you may be able to continue to use the current version of tools or IP with this license, you will not be eligible for any updates or new releases.
Running DRC as a precondition to command route_design
INFO: [DRC 23-27] Running DRC with 2 threads
WARNING: [DRC 23-20] Rule violation (PLIO-7) Placement Constraints Check for IO constraints - An IO Bus FIXED_IO_mio[53:0] with more than one IO standard is found. Components associated with this bus are:  FIXED_IO_mio[53] of IOStandard LVCMOS18; FIXED_IO_mio[52] of IOStandard LVCMOS18; FIXED_IO_mio[51] of IOStandard LVCMOS18; FIXED_IO_mio[50] of IOStandard LVCMOS18; FIXED_IO_mio[49] of IOStandard LVCMOS18; FIXED_IO_mio[48] of IOStandard LVCMOS18; FIXED_IO_mio[47] of IOStandard LVCMOS18; FIXED_IO_mio[46] of IOStandard LVCMOS18; FIXED_IO_mio[45] of IOStandard LVCMOS18; FIXED_IO_mio[44] of IOStandard LVCMOS18; FIXED_IO_mio[43] of IOStandard LVCMOS18; FIXED_IO_mio[42] of IOStandard LVCMOS18; FIXED_IO_mio[41] of IOStandard LVCMOS18; FIXED_IO_mio[40] of IOStandard LVCMOS18; FIXED_IO_mio[39] of IOStandard LVCMOS18; FIXED_IO_mio[38] of IOStandard LVCMOS18; FIXED_IO_mio[37] of IOStandard LVCMOS18; FIXED_IO_mio[36] of IOStandard LVCMOS18; FIXED_IO_mio[35] of IOStandard LVCMOS18; FIXED_IO_mio[34] of IOStandard LVCMOS18; FIXED_IO_mio[33] of IOStandard LVCMOS18; FIXED_IO_mio[32] of IOStandard LVCMOS18; FIXED_IO_mio[31] of IOStandard LVCMOS18; FIXED_IO_mio[30] of IOStandard LVCMOS18; FIXED_IO_mio[29] of IOStandard LVCMOS18; FIXED_IO_mio[28] of IOStandard LVCMOS18; FIXED_IO_mio[27] of IOStandard LVCMOS18; FIXED_IO_mio[26] of IOStandard LVCMOS18; FIXED_IO_mio[25] of IOStandard LVCMOS18; FIXED_IO_mio[24] of IOStandard LVCMOS18; FIXED_IO_mio[23] of IOStandard LVCMOS18; FIXED_IO_mio[22] of IOStandard LVCMOS18; FIXED_IO_mio[21] of IOStandard LVCMOS18; FIXED_IO_mio[20] of IOStandard LVCMOS18; FIXED_IO_mio[19] of IOStandard LVCMOS18; FIXED_IO_mio[18] of IOStandard LVCMOS18; FIXED_IO_mio[17] of IOStandard LVCMOS18; FIXED_IO_mio[16] of IOStandard LVCMOS18; FIXED_IO_mio[15] of IOStandard LVCMOS33; FIXED_IO_mio[14] of IOStandard LVCMOS33; FIXED_IO_mio[13] of IOStandard LVCMOS33; FIXED_IO_mio[12] of IOStandard LVCMOS33; FIXED_IO_mio[11] of IOStandard LVCMOS33; FIXED_IO_mio[10] of IOStandard LVCMOS33; FIXED_IO_mio[9] of IOStandard LVCMOS33; FIXED_IO_mio[8] of IOStandard LVCMOS33; FIXED_IO_mio[7] of IOStandard LVCMOS33; FIXED_IO_mio[6] of IOStandard LVCMOS33; FIXED_IO_mio[5] of IOStandard LVCMOS33; FIXED_IO_mio[4] of IOStandard LVCMOS33; FIXED_IO_mio[3] of IOStandard LVCMOS33; FIXED_IO_mio[2] of IOStandard LVCMOS33; FIXED_IO_mio[1] of IOStandard LVCMOS33; FIXED_IO_mio[0] of IOStandard LVCMOS33;
INFO: [Vivado_Tcl 4-198] DRC finished with 0 Errors, 1 Warnings
INFO: [Vivado_Tcl 4-199] Please refer to the DRC report (report_drc) for more information.


Starting Routing Task
INFO: [Route 35-254] Multithreading enabled for route_design using a maximum of 2 CPUs

Phase 1 Build RT Design
Phase 1 Build RT Design | Checksum: 55af47a8

Time (s): cpu = 00:00:33 ; elapsed = 00:00:30 . Memory (MB): peak = 1037.750 ; gain = 135.238

Phase 2 Router Initialization
INFO: [Route 35-64] No timing constraints were detected. The router will operate in resource-optimization mode.

Phase 2.1 Pre Route Cleanup
Phase 2.1 Pre Route Cleanup | Checksum: 55af47a8

Time (s): cpu = 00:00:33 ; elapsed = 00:00:30 . Memory (MB): peak = 1041.715 ; gain = 139.203
 Number of Nodes with overlaps = 0
Phase 2 Router Initialization | Checksum: 1ab00b4cb

Time (s): cpu = 00:00:34 ; elapsed = 00:00:30 . Memory (MB): peak = 1045.371 ; gain = 142.859

Phase 3 Initial Routing
 Number of Nodes with overlaps = 0
Phase 3 Initial Routing | Checksum: b21fa480

Time (s): cpu = 00:00:34 ; elapsed = 00:00:30 . Memory (MB): peak = 1045.371 ; gain = 142.859

Phase 4 Rip-up And Reroute

Phase 4.1 Global Iteration 0
Phase 4.1 Global Iteration 0 | Checksum: b21fa480

Time (s): cpu = 00:00:34 ; elapsed = 00:00:30 . Memory (MB): peak = 1045.371 ; gain = 142.859

Phase 4.2 Global Iteration 1
Phase 4.2 Global Iteration 1 | Checksum: b21fa480

Time (s): cpu = 00:00:34 ; elapsed = 00:00:30 . Memory (MB): peak = 1045.371 ; gain = 142.859

Phase 4.3 Global Iteration 2
Phase 4.3 Global Iteration 2 | Checksum: b21fa480

Time (s): cpu = 00:00:34 ; elapsed = 00:00:30 . Memory (MB): peak = 1045.371 ; gain = 142.859

Phase 4.4 Global Iteration 3
Phase 4.4 Global Iteration 3 | Checksum: b21fa480

Time (s): cpu = 00:00:34 ; elapsed = 00:00:30 . Memory (MB): peak = 1045.371 ; gain = 142.859

Phase 4.5 Global Iteration 4
Phase 4.5 Global Iteration 4 | Checksum: b21fa480

Time (s): cpu = 00:00:34 ; elapsed = 00:00:30 . Memory (MB): peak = 1045.371 ; gain = 142.859
Phase 4 Rip-up And Reroute | Checksum: b21fa480

Time (s): cpu = 00:00:34 ; elapsed = 00:00:30 . Memory (MB): peak = 1045.371 ; gain = 142.859

Phase 5 Delay and Skew Optimization
Phase 5 Delay and Skew Optimization | Checksum: b21fa480

Time (s): cpu = 00:00:34 ; elapsed = 00:00:30 . Memory (MB): peak = 1045.371 ; gain = 142.859

Phase 6 Post Hold Fix
Phase 6 Post Hold Fix | Checksum: b21fa480

Time (s): cpu = 00:00:34 ; elapsed = 00:00:30 . Memory (MB): peak = 1045.371 ; gain = 142.859

Phase 7 Route finalize

Router Utilization Summary
  Global Vertical Routing Utilization    = 0.0367609 %
  Global Horizontal Routing Utilization  = 0.0474983 %
  Routable Net Status*
  *Does not include unroutable nets such as driverless and loadless.
  Run report_route_status for detailed report.
  Number of Failed Nets               = 0
  Number of Unrouted Nets             = 0
  Number of Partially Routed Nets     = 0
  Number of Node Overlaps             = 0

Congestion Report
North Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions.
South Dir 1x1 Area, Max Cong = 16.2162%, No Congested Regions.
East Dir 1x1 Area, Max Cong = 29.4118%, No Congested Regions.
West Dir 1x1 Area, Max Cong = 17.6471%, No Congested Regions.
Phase 7 Route finalize | Checksum: b21fa480

Time (s): cpu = 00:00:34 ; elapsed = 00:00:30 . Memory (MB): peak = 1045.371 ; gain = 142.859

Phase 8 Verifying routed nets

 Verification completed successfully
Phase 8 Verifying routed nets | Checksum: b21fa480

Time (s): cpu = 00:00:34 ; elapsed = 00:00:30 . Memory (MB): peak = 1046.293 ; gain = 143.781

Phase 9 Depositing Routes
Phase 9 Depositing Routes | Checksum: b21fa480

Time (s): cpu = 00:00:34 ; elapsed = 00:00:30 . Memory (MB): peak = 1046.293 ; gain = 143.781
INFO: [Route 35-16] Router Completed Successfully

Time (s): cpu = 00:00:34 ; elapsed = 00:00:30 . Memory (MB): peak = 1046.293 ; gain = 143.781

Routing Is Done.
INFO: [Common 17-83] Releasing license: Implementation
44 Infos, 2 Warnings, 0 Critical Warnings and 0 Errors encountered.
route_design completed successfully
route_design: Time (s): cpu = 00:00:35 ; elapsed = 00:00:31 . Memory (MB): peak = 1046.293 ; gain = 148.934
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.080 . Memory (MB): peak = 1046.293 ; gain = 0.000
INFO: [DRC 23-27] Running DRC with 2 threads
INFO: [Coretcl 2-168] The results of DRC are in file C:/XLX/MZCC_ARD_7020/MZCC_ARD_7020.runs/impl_2/tutorial_wrapper_drc_routed.rpt.
INFO: [Timing 38-91] UpdateTimingParams: Speed grade: -1, Delay Type: min_max.
INFO: [Timing 38-191] Multithreading enabled for timing update using a maximum of 2 CPUs
WARNING: [Timing 38-313] There are no user specified timing constraints. Timing constraints are needed for proper timing analysis.
WARNING: [Power 33-232] No user defined clocks were found in the design!
Resolution: Please specify clocks using create_clock/create_generated_clock for sequential elements. For pure combinatorial circuits, please specify a virtual clock, otherwise the vectorless estimation might be inaccurate
Running Vector-less Activity Propagation...

Finished Running Vector-less Activity Propagation
INFO: [Common 17-206] Exiting Vivado at Wed Jul 29 16:34:26 2015...
