2016 IoT Sensor Fusion Winners:
The University of Advancing Technology
IoT Sensor Fusion Challenge - The game formerly known as Digital Design Dilemma has gotten a facelift! In this challenge, teams will design and demonstrate a solution using software and gateway with component hardware to achieve a specific set of criteria revealed at the starting time. Completion of this challenge will result in the aggregation of real-time information from a collection of sensors within an All Programmable edge node, making it available for consumption in a cloud-based analytics application. Students will compile a presentation of their solution and demonstrate their work in front of a panel of judges.
In this challenge, small design teams will develop and demonstrate a solution using software and gateway, sensor and component hardware to achieve a specific set of criteria revealed at the starting time. Completion of this challenge will result in the aggregation of real-time information from a collection of sensors within an All Programmable edge node, making it available for consumption in a cloud-based analytics application. Students will compile a presentation of their solution and demonstrate their work in front of a panel of judges.
NOTE: This event is targeted to students with experience or classwork in digital design, programming or similar fields of study.
Example of Past Design Challenge: Below is a sample of a previous year's Digital Design Challenge. This year's competition will be different; however, if the student has the capability or skillset found in this example they should feel confident in participating in this year's IoT Sensor Fusion Challenge!
Your task: You are to design a 60-second clock, which displays the current time in seconds on a two-digit seven-segment display. Your clock should operate as follows:
- Upon reset (RESET pushbutton) the clock should display "00" and begin counting.
- The clock shall run continuously, changing on one second intervals unless manually paused or reset.
- The count shall be displayed in decimal format.
- While a finger is hold on the PUSH_A button, the clock shall pause with its current value and then continue counting with the next value when the finger is removed.
- You may use any of the board's clock sources so long as the displayed clock counts in one second intervals. You will be asked to demonstrate the accuracy of your clock.
- You may implement your design with VHDL, Verilog or schematics. There will be no penalty for the methodology used.
- You will demonstrate and give a 20-minute presentation on your design.
- At the official deadline, you must turn in your presentation and FPGA programming file on a USB memory stick, which will be returned to you at the time of your presentation. The presentation room will have an identical laptop and set of hardware.
- Electrical computer science and computer system engineering
- Electronics and manufacturing disciplines
Familiarity with Digital Logic Design, Xilinx Vivado Design Suite an FPGA development board
Avnet will provide laptops preloaded with:
- Microsoft PowerPoint (or equivalent presentation software)
- Development kits with documentation and additional hardware as needed for the design
- A USB memory stick for each team to turn in their design and presentation
Students are free to bring other resources (textbooks, notes, etc.) that might be helpful.
This schedule is subject to change; however, this will be an all-day event.
Saturday, April 2, 2016, The University of Advancing Technology
Event kick off - 8 a.m. (please arrive 30 minutes prior for registration)
Complete the design challenge - 8 a.m. – noon
(all projects are due at noon SHARP)
Lunch - noon - 1 p.m.
Pre-judging if necessary - noon - 12:30 p.m.
- 12:30 p.m. - 3 p.m.
(time slots will be randomly assigned to all teams)
Each winning team member will receive $1,000 scholarship.